Abstract: Leakage current in semiconductor logic can be minimized using the present systems and techniques. For example, a CMOS circuit for low leakage battery operation can connect a real time clock to the power supply when available or to a low leakage source when the power supply is not available.

Abstract: A processor is disclosed that can map a request from a central processing unit that uses memory-mapped input-output space to a second processing domain, such as a multithreaded processing domain. A request addressed to the input-output space of the central processing unit is converted to a corresponding command that simulates an operation between components in the multithreaded processing domain. The command is executed in the multithreaded processing domain. Information is accessed according to the request in response to executing the command.

Abstract: An integrated circuit includes a random access memory (RAM) storage and a controller both located on one semiconductor chip. The controller is coupled to read data from and write data to the RAM storage. The controller is programmable to perform bitwise operations on data words stored in the RAM.

Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. A program thread communication scheme for packet processing is also described.

Abstract: A device to change the ordering of datums in a packet from a storage device to a pre-determined ordering according to their addresses. The device has a first circuit to receive and process address information to determine a data ordering of data associated with the address information; and a second circuit to reorder the data into ordered packets in the predetermined ordering. This device can be used to efficiently transfer graphic data through the AGP bus in a computer.

Abstract: Receiving bytes of data from a media device includes issuing N consecutive requests, each for M bytes, to the media device and receiving N−1 responses of M bytes of data from the media device.

Abstract: A CMOS circuit for low leakage battery operation connects the real time clock to the power supply when available or to a low leakage source when the power supply is not available.

Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.

Abstract: A method includes pushing a datum onto a stack by a first processor and popping the datum off the stack by a second processor.

Abstract: An organic light emitting diode (OLED) display includes an array of OLED pixels that generate heat and an array of thermally conductive elements positioned between the OLED pixels and a thermally conductive back panel. In one embodiment of the invention, the thermally conductive elements may be solder joints deposited over cathode contacts and anode contacts at each OLED pixel. The solder joints provide a path of low thermal resistance from the OLED pixels to the back panel. Also, the solder joints may serve as an array of electrical connections from back panel interconnects to the cathode lines and anode lines.

Abstract: An integrated circuit includes a random access memory (RAM) storage and a controller both located on one semiconductor chip. The controller is coupled to read data from and write data to the RAM storage. The controller is programmable to perform bitwise operations on data words stored in the RAM.

Abstract: A system has a processor with multiple states, including an awake state and a sleep state, a memory subsystem including a memory controller and memory devices, and a second memory. The system uses software in the second memory to initialize the memory controller upon a transition from a sleep state to an awake state. The system detects a wake event trigger, and in response to the wake event trigger, executes software stored in the second memory to initialize the memory controller, and then executes software out of the first memory after the initialization.

Abstract: A parallel, multi-threaded processor system and technique for arbitrating command requests is described. The system includes a plurality of microengines, a plurality of shared system resources and a global command arbiter. The global command arbiter uses a command request protocol that is based on the shared system resources and command type to grant or deny a microengine command request for a shared resource.

Abstract: Computer systems having two processors of different clock frequencies and different levels of power consumption. An interface circuit can select one of the two processors to operate at a time to reduce power consumption without compromising the system performance.

Abstract: A domino logic circuit contained within an integrated circuit includes a dynamic logic circuit and an intermediate logic circuit. The intermediate logic circuit includes a pull-up transistor having a source terminal coupled to a source voltage line and an n-block transistor having a source terminal connected to a low ground voltage line.

Abstract: A shielded socket includes a conducting plate including a plurality of apertures, and an insulating layer. The insulating layer surrounds the conducting plate and lines at least one aperture. In an implementation, the conducting plate includes at least one grounding site.

Abstract: In general the invention features a disk drive carrier and a method for inserting a disk drive into a peripheral bay chassis. The disk drive carrier includes a base for receiving a disk drive into and a latching mechanism that is rotatably attached to the base. The rotatably mount permits a lever to rotate between an open position and a closed position. The lever includes a lower engagement point and an upper engagement point. The disk drive carrier can additionally include a downwardly movable release tab attached to the upper engagement point facilitating release of the engagement point from a P-Bay chassis. The disk drive carrier can also include an electromagnetic interference (EMI) shield to create a tight EMI seal in the front of a P-Bay chassis slot.

Abstract: In general the invention features a disk drive carrier and a method for inserting a disk drive into a peripheral bay chassis. The disk drive carrier includes a base for receiving a disk drive into and a latching mechanism that is rotatably attached to the base. The rotatably mount permits a lever to rotate between an open position and a closed position. The lever includes a lower engagement point and an upper engagement point. The disk drive carrier can additionally include a downwardly movable release tab attached to the upper engagement point facilitating release of the engagement point from a P-Bay chassis. The disk drive carrier can also include an electromagnetic interference (EMI) shield to create a tight EMI seal in the front of a P-Bay chassis slot.

Abstract: An integrated circuit includes a random access memory (RAM) storage and a controller both located on one semiconductor chip. The controller is coupled to read data from and write data to the RAM storage. The controller is programmable to perform bitwise operations on data words stored in the RAM.

Abstract: Managing memory access to random access memory includes fetching a read lock memory reference request and placing the read lock memory reference request at the end of a read lock miss queue if the read lock memory reference request is requesting access to an unlocked memory location and the read lock miss queue contains at least one read lock memory reference request.