Patents Assigned to Intel IP Corporation
  • Patent number: 11798123
    Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: October 24, 2023
    Assignee: Intel IP Corporation
    Inventors: Carsten Benthin, Sven Woop, Ingo Wald
  • Publication number: 20230139455
    Abstract: In one embodiment, an apparatus includes memory storing instructions and processing circuitry coupled to the memory. The processing circuitry is to implement the instructions to select a resource block group (RBG) size configuration from a set of RBG size configurations based on a bandwidth part (BWP) size. Each RBG size configuration is to indicate RBG sizes associated with respective ranges of BWP sizes, and the RBG sizes are to indicate a number of frequency-domain physical resource blocks (PRBs) for physical downlink shared channel (PDSCH) or physical uplink shared channel (PUSCH) transmissions. The processing circuitry is further to implement the instructions to allocate PRBs for communication between the gNB device and a user equipment (UE) device via the PDSCH or PUSCH transmissions based on the selected RBG size, and to encode downlink control information (DCI) that indicates the allocated PRBs for transmission to the UE device.
    Type: Application
    Filed: June 15, 2018
    Publication date: May 4, 2023
    Applicant: Intel IP Corporation
    Inventors: Debdeep Chatterjee, Sergey Panteleev, Hong He, Gang Xiong, Jeongho Jeon, Ajit Nimbalker, Joonyoung Cho
  • Publication number: 20230119093
    Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.
    Type: Application
    Filed: August 25, 2022
    Publication date: April 20, 2023
    Applicant: Intel IP Corporation
    Inventors: Carsten Benthin, Sven Woop, Ingo Wald
  • Publication number: 20220345762
    Abstract: For example, an apparatus may include a video encoder configured to encode video data into a parallel plurality of encoded video streams, the parallel plurality of encoded video streams including the video data encoded according to a respective plurality of different video bitrates; a selector configured to select, based on one or more parameters corresponding to a condition of a wireless communication link, a selected encoded video stream from the parallel plurality of encoded video streams; and a radio to transmit the selected encoded video stream over the wireless communication link.
    Type: Application
    Filed: September 16, 2018
    Publication date: October 27, 2022
    Applicant: INTEL IP CORPORATION
    Inventors: Yaniv Frishman, Ran Mor, Sharon Talmor-Marcovici
  • Patent number: 11443405
    Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: September 13, 2022
    Assignee: Intel IP Corporation
    Inventors: Carsten Benthin, Sven Woop, Ingo Wald
  • Patent number: 11380616
    Abstract: Fan Out Package-On-Package (PoP) assemblies in which a second chip is adhered to a non-active side of a first chip. An active side of the first chip embedded in a first package material may be electrically coupled through one or more redistribution layers that fan out to package interconnects on a first side of the POP. A second chip may be adhered, with a second package material, to the non-active side of the first chip. An active side of the second chip may be electrically coupled to the package interconnects through a via structure extending through the first package material. Second interconnects between the second chip, or a package thereof, may contact the via structure. Use of the second package material as an adhesive may improve positional stability of the second chip to facilitate wafer-level assembly techniques.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: July 5, 2022
    Assignee: Intel IP Corporation
    Inventors: David O'Sullivan, Bernd Waidhas, Thomas Huber
  • Patent number: 11323102
    Abstract: A multiphase signal generator includes an input port. Furthermore, the multiphase signal generator includes a plurality of phase shifters. Each phase shifter of the plurality of phase shifters is configured to provide an identical phase shift ??. At least one phase shifter is connected to the input port. Furthermore, the multiphase signal generator includes a first phase interpolator and at least a second phase interpolator. Each phase interpolator has a respective output terminal. Each phase interpolator is configured to weight a phase of a signal at a respective first input terminal of the phase interpolator with a respective first weighting factor wi,1 and to weight a phase of another signal at a respective second input terminal of the phase interpolator with a respective second weighting factor wi,2 to generate an interpolated phase signal at the respective output terminal of the phase interpolator. A first subset of the plurality of phase shifters includes n>1 serially connected phase shifters.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: May 3, 2022
    Assignee: Intel IP Corporation
    Inventors: Michael Kalcher, Daniel Gruber, Francesco Conzatti, Patrizia Greco
  • Publication number: 20220013473
    Abstract: An integrated circuit package shield comprising a frame comprising two or more segments, the segments to interlock with one another along a substrate and the segments comprising electrically conductive material to electrically couple to the substrate; and a lid to cover the frame, the lid comprising a conductive material to electrically couple to the substrate.
    Type: Application
    Filed: September 28, 2021
    Publication date: January 13, 2022
    Applicant: Intel IP Corporation
    Inventor: Rizwan Fazil
  • Publication number: 20210410024
    Abstract: An apparatus of an evolved NodeB (eNB) comprises one or more baseband processors to encode measurement gap configuration information including a measurement gap configuration information element MeasGapConfig to configure a network controlled small gap (NCSG) pattern for a user equipment (UE) device if the UE requires an NCSG and the UE is not configured with a primary secondary cell (PSCELL), and a memory to store the measurement gap configuration information.
    Type: Application
    Filed: February 2, 2018
    Publication date: December 30, 2021
    Applicant: Intel IP Corporation
    Inventors: Yang Tang, Candy Yiu, Rui Huang, Jie Cui, Shuang Tian
  • Publication number: 20210368420
    Abstract: This disclosure describes systems, methods, and devices related to deterministic backoffs and collision avoidance. A device may identify a first transmission received from a first device, wherein the first transmission is over a shared access medium. The device may identify a second transmission received from the first device, wherein the second transmission is over the shared access medium. The device may determine an available transmission slot between the first transmission and the second transmission. The device may transmit, during the available transmission slot, a third transmission.
    Type: Application
    Filed: June 26, 2018
    Publication date: November 25, 2021
    Applicant: Intel IP Corporation
    Inventors: Dave CAVALCANTI, Laurent CARIOU, Mohammad Mamunur RASHID
  • Publication number: 20210351859
    Abstract: An apparatus of a transmitter may include, for example, a Golay builder to build modulated Golay sequences for at least a non-EDMG Short Training Field (L-STF), and a non-EDMG Channel Estimation Field (L-CEF) of a PPDU; a scrambler to generate scrambled bits by scrambling bits of a non-EDMG header (L-header) and a data field of the PPDU; an encoder to encode the scrambled bits into encoded bits according to a low-density parity-check (LDDC) code; a constellation mapper to map the encoded bits into a stream of constellation points according to a constellation scheme; a spreader to spread the stream of constellation points according to a Golay sequence; and a transmit chain mapper to map a bit stream output from the Golay builder and the spreader to a plurality of transmit chains by applying a spatial expansion with relative cyclic shift over the plurality of transmit chains.
    Type: Application
    Filed: June 14, 2021
    Publication date: November 11, 2021
    Applicant: INTEL IP CORPORATION
    Inventors: Alexander Maltsev, Carlos Cordeiro, Artyom Lomayev, Michael Genossar, Claudio Da Silva
  • Publication number: 20210351817
    Abstract: Techniques to enable dynamic bandwidth management at the physical layer level while maintaining backwards compatibility in wireless systems is provided. Furthermore, techniques for reducing the occurrence of exposed nodes are provided. A transmitter may transmit a frame including an indication that a PHY layer sub-header defining a bandwidth associated with a channel is present. Furthermore, the transmitter may transmit a third frame after receiving a second frame from a receiver to indicate to legacy stations that the TXOP was successful.
    Type: Application
    Filed: March 24, 2021
    Publication date: November 11, 2021
    Applicant: Intel IP Corporation
    Inventors: Carlos Cordeiro, Assaf Kasher, Solomon Trainin
  • Publication number: 20210342968
    Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.
    Type: Application
    Filed: May 17, 2021
    Publication date: November 4, 2021
    Applicant: Intel IP Corporation
    Inventors: Carsten Benthin, Sven Woop, Ingo Wald
  • Patent number: 11158585
    Abstract: An integrated circuit package shield comprising a frame comprising two or more segments, the segments to interlock with one another along a substrate and the segments comprising electrically conductive material to electrically couple to the substrate; and a lid to cover the frame, the lid comprising a conductive material to electrically couple to the substrate.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: October 26, 2021
    Assignee: Intel IP Corporation
    Inventor: Rizwan Fazil
  • Publication number: 20210328709
    Abstract: Some demonstrative embodiments include apparatuses, devices, systems and methods of communicating a Physical Layer Protocol Data Unit (PPDU). For example, an Enhanced Directional Multi-Gigabit (DMG) (EDMG) station (STA) may be configured to encode a Physical Layer (PHY) Service Data Unit (PSDU) of at least one user in an EDMG PM Protocol Data Unit (PPDU) according to an EDMG Low-Density Parity-Check (LDPC) encoding scheme, which is based at least on a count of one or more spatial streams for transmission to the user; and transmit the EDMG PPDU in a transmission over a channel bandwidth in a frequency band above 45 Gigahertz (GHz).
    Type: Application
    Filed: June 23, 2021
    Publication date: October 21, 2021
    Applicant: INTEL IP CORPORATION
    Inventors: Artyom Lomayev, Alexander Maltsev, Michael Genossar, Claudio Da Silva, Carlos Cordeiro
  • Patent number: 11152997
    Abstract: Briefly, in accordance with one or more embodiments, an apparatus of a user equipment (UE) comprising circuitry to receive a Beamforming Reference Signal (BRS) transmission from an evolved NodeB (eNB) via one or more transmission beams, divide the one or more transmission beams into one or more transmission beam sets, wherein a transmission beam set comprises a number of consecutive orthogonal frequency-division multiplexing (OFDM) symbols, scan consecutive receiving beams for corresponding transmission beam sets to obtain channel measurements to select a transmission beam and a receiving beam based at least in part on the channel measurements, and receive transmissions from the eNB using the selected transmission beam and the selected receiving beam.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: October 19, 2021
    Assignee: INTEL IP CORPORATION
    Inventors: Yushu Zhang, Gang Xiong, Yuan Zhu, Ralf Bendlin, Jong-Kae Fwu
  • Publication number: 20210321324
    Abstract: An application management apparatus for controlling tasks, including a task split and response merge circuit configured to divide an application into a plurality of tasks and associate respective Key Performance Indicator (KPI) attributes to the plurality of tasks; and a task management circuit configured to allocate each of the plurality of tasks to a first or second Radio Access Technology (RAT) based on the KPI attributes, and to derive a plurality of task responses from the first or second RATs to which the respective plurality of tasks are allocated, wherein the task split and response merge circuit is further configured to merge the task responses to select the first or second RAT to run the application.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 14, 2021
    Applicant: Intel IP Corporation
    Inventors: Biljana Badic, Markus Dominik Mueck, Zhibin Yu, Bernhard Raaf, Dave Cavalcanti, Ana Lucia A. Pinheiro, Pinheiro
  • Publication number: 20210320071
    Abstract: An integrated circuit package shield comprising a frame comprising two or more segments, the segments to interlock with one another along a substrate and the segments comprising electrically conductive material to electrically couple to the substrate; and a lid to cover the frame, the lid comprising a conductive material to electrically couple to the substrate.
    Type: Application
    Filed: March 27, 2018
    Publication date: October 14, 2021
    Applicant: Intel IP Corporation
    Inventor: Rizwan Fazil
  • Publication number: 20210297867
    Abstract: Measurement configuration techniques for wideband coverage enhancement (WCE)-capable devices are described. According to various such techniques, a WCE-capable UE may be configured to recognize and apply distinct respective discovery signal measurement timing configurations (DMTCs) for WCE discovery reference signal (DRS) measurements and non-WCE DRS measurements. In some embodiments, the DMTC for WCE DRS measurements may specify a longer measurement periodicity for WCE DRS measurements than that applicable to non-WCE DRS measurements. In some embodiments, the DMTC for WCE DRS measurements may specify a larger measurement window for WCE DRS measurements than that applicable to non-WCE DRS measurements. In some embodiments, the WCE-capable UE may be configured to recognize and distinct respective measurement gap configurations for WCE and non-WCE measurements. Other embodiments are described and claimed.
    Type: Application
    Filed: May 10, 2018
    Publication date: September 23, 2021
    Applicant: INTEL IP CORPORATION
    Inventors: Huaning NIU, Seau LIM, Anthony LEE, Candy YIU, Youn Hyoung HEO
  • Patent number: 11128505
    Abstract: Methods, apparatuses, and computer readable media include an apparatus of an access point (AP) or station (STA) comprising processing circuitry configured to decode a legacy preamble of a physical layer (PHY) protocol data unit (PPDU), determine whether the legacy preamble comprises an indication that the PPDU is an extremely-high throughput (EHT) PPDU, and in response to the determination indicating the PPDU is the EHT PPDU, decode the EHT PPDU. Some embodiments determine a spatial stream resource allocation based on a row of a spatial configuration table, a row of a frequency resource unit table, a number of stations, and location of the station relative to the number of stations in user fields of an EHT-signal (SIG) field. To accommodate 16 spatial streams, some embodiments extend the length of the packet extension field, extend signaling of a number of spatial streams, and/or extend a number of EHT-SIG symbols.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: September 21, 2021
    Assignee: Intel Corporation and Intel IP Corporation
    Inventors: Xiaogang Chen, Thomas J. Kenney, Shahrnaz Azizi, Robert J. Stacey, Laurent Cariou, Qinghua Li, Feng Jiang