Abstract: The stack-gate flash memory cell structure of the present invention comprises a floating-gate structure with a thinner floating-gate layer being formed in a central portion by using a spacer-formation technique; an implanted region being formed in the central portion of a channel for adjusting threshold-voltage and forming a punch-through stop; and a highly conductive control-gate structure spaced with an intergate-dielectric layer being formed over the floating-gate structure. The contactless NOR-type array of the present invention comprises a plurality of common-source conductive bus lines and a plurality of planarized common-drain conductive islands being integrated with a plurality of metal bit-lines. The contactless parallel common-source/drain bit-line array comprises a plurality of common-source/drain conductive bit-lines and a plurality of metal word-lines being integrated with a plurality of planarized control-gate conductive islands.

Abstract: A stacked-gate cell structure having a tapered floating-gate layer and a laterally graded source/drain diffusion profile is implemented to form NAND cell strings over a self-aligned STI structure having a high coupling ratio. The paired string select lines and the paired ground select lines being formed over one-side tapered floating-gate layers are simultaneously defined by a spacer formation technique and are therefore scalable. Each of common-source conductive bus lines is formed over a first flat bed between a pair of sidewall dielectric spacers being formed over sidewalls of the paired ground select lines. A plurality of planarized common-drain conductive islands are formed over common-drain diffusion regions between another pair of sidewall dielectric spacers being formed over sidewalls of the paired string select lines and are patterned simultaneously with a plurality of metal bit-lines by using a masking photoresist step.

Abstract: A self-aligned trench-type DRAM structure comprising a self-aligned DRAM capacitor structure and a self-aligned DRAM transistor structure are disclosed by the present invention, in which the self-aligned DRAM capacitor structure comprises a deep-trench capacitor region and a shallow-trench-isolation region being defined by a spacer technique and the self-aligned DRAM transistor structure comprises a scalable gate-stack region and a common-drain region being defined by another spacer technique. The self-aligned trench-type DRAM structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized conductive-gate islands and a plurality of common-drain conductive bit-lines.

Abstract: The stack-type DRAM memory structure of the present invention comprises a plurality of self-aligned thin third conductive islands over shallow heavily-doped source diffusion regions without dummy transistors to obtain a cell size of 6F2 or smaller; a rectangular tube-shaped cavity having a conductive island formed above a nearby transistor-stack being formed over each of the self-aligned thin third conductive islands to offer a larger surface area for forming a high-capacity DRAM capacitor of the present invention; a planarized third conductive island being formed between a pair of first sidewall dielectric spacers and on each of shallow heavily-doped common-drain diffusion regions to offer a larger contact area and a higher contact integrity; and a plurality of planarized conductive contact-islands being formed over the planarized third conductive islands to eliminate the aspect-ratio effect and being patterned and etched simultaneously with a plurality of bit lines.

Abstract: A scaled MOSFET device of the present invention comprises a shallow-trench-isolation structure being formed on a semiconductor substrate; a conductive-gate structure having a pair of second conductive sidewall spacers formed over each inner sidewall of a gate region and on a first conductive layer and first raised field-oxide layers for forming an implant region in a central portion of a channel and a planarized third conductive layer for forming a salicide-gate structure or a polycide-gate structure; a buffer-dielectric layer being formed over each sidewall of the conductive-gate structure for forming lightly-doped source/drain diffusion regions; a first sidewall dielectric spacer being formed over each sidewall of the buffer-dielectric layers for forming heavily-doped source/drain diffusion regions; and a second sidewall dielectric spacer being formed over each sidewall of the first sidewall dielectric spacers for forming a self-aligned silicidation contact over each of the heavily-doped source/drain diffus

Abstract: A self-aligned lateral-transistor DRAM cell structure is disclosed by the present invention, in which a trench structure comprises a trench region and a trench-isolation region being formed in a side portion of the trench region and a self-aligned lateral-transistor structure comprises a merged common-source diffusion region, a self-aligned gate-stack region, and a self-aligned common-drain diffusion region being formed in another side portion of the trench region by using spacer-formation techniques. The unit cell size of the self-aligned lateral-transistor DRAM cell structure can be fabricated to be equal to 6 F2 or smaller. The self-aligned lateral-transistor DRAM cell structure is used to implement two contactless DRAM arrays for high-speed read and write operations.

Abstract: The nanometer-gate MOSFET device of the present invention comprises a shallow-trench-isolation structure; a pair of second conductive sidewall spacers being formed over each inner sidewall of a gate region and on a portion of a first conductive layer and a first raised field-oxide layers for forming an implant region in a central portion of a channel; a buffer-oxide layer being formed over each sidewall of the gate region for forming lightly-doped source/drain diffusion regions; a first sidewall dielectric spacer being formed over each sidewall of the buffer-oxide layers for forming heavily-doped source/drain diffusion regions; a second sidewall dielectric spacer being formed over each sidewall of the first sidewall dielectric spacers for forming a metal-silicide layer over each of heavily-doped source/drain diffusion regions; and a highly conductive-gate structure being formed in the gate region.

Abstract: The scalable stack-type DRAM memory structure of the present invention comprises a scalable DRAM transistor structure and a scalable DRAM capacitor structure. The scalable DRAM transistor structure comprises a plurality of transistor-stacks, a plurality of common-drain regions, and a plurality of source regions being formed over a shallow-trench-isolation structure without a dummy-transistor structure by using a spacer-formation technique. The scalable DRAM capacitor structure comprises a plurality of rectangular tube-shaped cavities being formed over thin fourth conductive islands to form a high-capacity DRAM capacitor for each of DRAM cells; and a plurality of planarized conductive contact-islands over planarized third conductive islands being patterned and simultaneously etched with a plurality of bit-lines for forming a contactless DRAM memory. The cell size of a DRAM cell is scalable and can be made to be smaller than 6F2.

Abstract: A vertical DRAM cell structure is disclosed by the present invention, in which a trench structure comprises a deep-trench region having a vertical transistor and a second-type STI region being formed in a side portion of the deep-trench region and a common-drain structure comprises different implant regions under a common-drain diffusion region being formed in another side portion of the deep-trench region. The vertical DRAM cell structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands and a plurality of common- drain conductive bit-lines.

Abstract: A self-aligned lateral-transistor DRAM cell structure is disclosed by the present invention, in which a trench structure comprises a trench region and a trench-isolation region being formed in a side portion of the trench region and a self-aligned lateral-transistor structure comprises a merged common-source diffusion region, a self-aligned gate-stack region, and a self-aligned common-drain diffusion region being formed in another side portion of the trench region by using spacer-formation techniques. The unit cell size of the self-aligned lateral-transistor DRAM cell structure can be fabricated to be equal to 6F2 or smaller. The self-aligned lateral-transistor DRAM cell structure is used to implement two contactless DRAM arrays for high-speed read and write operations.

Abstract: A self-aligned vertical transistor DRAM structure comprising a self-aligned trench structure and a self-aligned common-drain structure are disclosed by the present invention, in which the self-aligned trench structure comprises a deep-trench capacitor region having a vertical transistor and a second-type shallow-trench-isolation region being defined by a spacer technique and the self-aligned common-drain structure comprises a common-drain region being defined by another spacer technique. The self-aligned vertical transistor DRAM structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands and a plurality of common-drain conductive bit-lines.

Abstract: A self-aligned vertical transistor DRAM structure comprising a self-aligned trench structure and a self-aligned common-drain structure are disclosed by the present invention, in which the self-aligned trench structure comprises a deep-trench capacitor region having a vertical transistor and a second-type shallow-trench-isolation region being defined by a spacer technique and the self-aligned common-drain structure comprises a common-drain region being defined by another spacer technique. The self-aligned vertical transistor DRAM structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands and a plurality of common-drain conductive bit-lines.

Abstract: A vertical transistor DRAM structure is disclosed by the present invention, in which a trench structure comprises a deep-trench region having a vertical transistor and a second-type shallow-trench-isolation region being formed in a side portion of the deep-trench region and a common-drain structure comprises different implant regions being formed under a common-drain diffusion region in another side portion of the deep-trench region. The vertical transistor DRAM structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands and a plurality of common- drain conductive bit-lines.

Abstract: A self-aligned trench-type DRAM structure comprising a self-aligned DRAM capacitor structure and a self-aligned DRAM transistor structure are disclosed by the present invention, in which the self-aligned DRAM capacitor structure comprises a deep-trench capacitor region and a shallow-trench-isolation region being defined by a spacer technique and the self-aligned DRAM transistor structure comprises a scalable gate-stack region and a common-drain region being defined by another spacer technique. The self-aligned trench-type DRAM structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized conductive-gate islands and a plurality of common-drain conductive bit-lines.

Abstract: The scalable stack-type DRAM memory structure of the present invention comprises a scalable DRAM transistor structure and a scalable DRAM capacitor structure. The scalable DRAM transistor structure comprises a plurality of transistor-stacks, a plurality of common-drain regions, and a plurality of source regions being formed over a shallow-trench-isolation structure without a dummy-transistor structure by using a spacer-formation technique. The scalable DRAM capacitor structure comprises a plurality of rectangular tube-shaped cavities being formed over thin fourth conductive islands to form a high-capacity DRAM capacitor for each of DRAM cells; and a plurality of planarized conductive contact-islands over planarized third conductive islands being patterned and simultaneously etched with a plurality of bit-lines for forming a contactless DRAM memory. The cell size of a DRAM cell is scalable and can be made to be smaller than 6F2.

Abstract: A scaled MOSFET device of the present invention comprises a shallow-trench-isolation structure being formed on a semiconductor substrate; a conductive-gate structure having a pair of second conductive sidewall spacers formed over each inner sidewall of a gate region and on a first conductive layer and first raised field-oxide layers for forming an implant region in a central portion of a channel and a planarized third conductive layer for forming a salicide-gate structure or a polycide-gate structure; a buffer-dielectric layer being formed over each sidewall of the conductive-gate structure for forming lightly-doped source/drain diffusion regions; a first sidewall dielectric spacer being formed over each sidewall of the buffer-dielectric layers for forming heavily-doped source/drain diffusion regions; and a second sidewall dielectric spacer being formed over each sidewall of the first sidewall dielectric spacers for forming a self-aligned silicidation contact over each of the heavily-doped source/drain diffus

Abstract: The nanometer-gate MOSFET device of the present invention comprises a shallow-trench-isolation structure; a pair of second conductive sidewall spacers being formed over each inner sidewall of a gate region and on a portion of a first conductive layer and a first raised field-oxide layers for forming an implant region in a central portion of a channel; a buffer-oxide layer being formed over each sidewall of the gate region for forming lightly-doped source/drain diffusion regions; a first sidewall dielectric spacer being formed over each sidewall of the buffer-oxide layers for forming heavily-doped source/drain diffusion regions; a second sidewall dielectric spacer being formed over each sidewall of the first sidewall dielectric spacers for forming a metal-silicide layer over each of heavily-doped source/drain diffusion regions; and a highly conductive-gate structure being formed in the gate region.

Abstract: A scalable vertical DRAM cell structure comprising a scalable trench region and a self-aligned common-drain diffusion region are disclosed by the present invention, in which the scalable trench region comprises a deep-trench region having a vertical transistor and a second-type STI region being defined by a spacer technique. The scalable vertical DRAM cell structure can offer a DARM cell size equal to or smaller than 4F2 and is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands over common-gate conductive connector islands and a plurality of common-drain conductive bit-lines.