Abstract: A method for responding to a command sequence includes receiving a signal from a host carrying a plurality of commands in the command sequence, detecting a non-consecutive clock associated with a start of a current command in the command sequence, and generating a control signal in an active state to indicate detection of the non-consecutive clock.

Abstract: An apparatus includes a detector circuit and a data buffer. The detector circuit may be configured to (i) identify a start of a command sequence associated with a directed access to a memory system and (ii) generate a control signal indicating a non-consecutive clock associated with the start of the command sequence. The data buffer circuit may be configured to initialize a condition of a receiver circuit in response to the control signal prior to reception of a first data bit associated with the command sequence.

Abstract: Variable feedback architecture and control techniques for variable gain amplifiers (VGAs) concurrently maintain, across a wide range of VGA gain settings, minimal input and output impedance variations, a low noise figure, low rates of change in noise figure, high signal-to-noise ratio (SNR), high quality of service (QoS), low distortion, high and relatively constant output third order intercept point (i.e., IP3 or TOI). Variable feedback counteracts impedance variations caused by gain variations. Compared to conventional high performance VGAs, noise figure is lower (e.g. 3 dB lower at maximum gain and 12 dB lower at minimum gain) and relatively constant, IP3 is higher and relatively constant, small signal third order intermodulation signal (IM3) tone slope is relatively constant and input and output impedances are relatively constant. As gain decreases, the noise figure advantage is nearly dB per dB compared to conventional high performance VGAs.

Abstract: Methods and systems for peak detection as part of automatic gain control in high-speed communications are provided. A peak detection system uses a portion of an input signal to generate a reference signal for comparison with the input signal. The comparison produces a differential error signal that is in turn used to produce one or more full swing pulses based on the comparison. A pulse counter counts the pulses, and if the count in a single clock cycle is above a determined threshold, a binary error signal is set to indicate a need for correction.

Abstract: A reference signal generator includes an integrated circuit substrate having a semiconductor resonator therein. The resonator includes an inductor extending adjacent a first surface of the integrated circuit substrate. A vertically-stacked composite of at least first and second electrically insulating dielectric layers is provided on the integrated circuit substrate. The vertically-stacked composite covers a portion of the first surface, which extends opposite the inductor. A first electrically conductive shielding layer is provided on a portion of the second electrically insulating dielectric layer extending opposite the inductor. The first electrically conductive shielding layer may encapsulate exposed portions of the first and second electrically insulating dielectric layers. The shielding layer may operate as an electromagnetic shield between the inductor and an external structure, such as an integrated circuit package, and also shield against environmental contamination (e.g.

Abstract: A method of modeling the output drivers in an integrated circuit, for example a serializer/deserializer circuit, is provided. In accordance with embodiments of the invention, at least one parameter of the circuit is physically measured and a behavioral model utilizing that parameter is constructed. The behavioral model can then be utilized to predict the behavior of the integrated circuit output drivers.

Abstract: A method and apparatus for generating a random bit stream in true random number generator fashion are described. Two periodic signals are employed in generating the random bit stream. A first periodic signal having preferably an approximately fifty percent duty cycle and jitter induced by supply and substrate noise is sampled by a second periodic signal that is relatively jitter-free and of a lower frequency than the first periodic signal.

Abstract: In a system having independently-clocked job-performing circuits (e.g., payload processors) and independently-clocked job-ordering circuits (e.g., request and payload suppliers), coordinating mechanisms are provided for coordinating exchanges between the independently-clocked circuits. The coordinating mechanisms include those that use transmitted time-stamps for scheduling contention-free performances within the job-performing circuits of requested jobs. The coordinating mechanisms additionally or alternatively include static and dynamic rate constraining means that are configured to prevent a faster-clocked one of the independently-clocked circuits from overwhelming a more slowly-clocked other of the independently-clocked circuits. In one implementation, independently-clocked telecommunication-shelves house a distributed set of line cards and switch cards.

Abstract: A phase locked loop (PLL) circuit includes a controlled oscillator circuit that is operative to generate an output clock signal responsive to an oscillator control signal according to a plurality of selectable transfer functions, and an oscillator control signal generator circuit that is operative to generate the oscillator control signal responsive to the output clock signal and a reference clock signal. The PLL circuit further includes a transfer function control circuit operative to transition operation of the controlled oscillator from a first one of the transfer functions to a second one of the transfer functions responsive to the oscillator control signal.

Abstract: Embodiments of the present invention may provide methods of controlling a memory device and memory devices including a memory array having an internal address input which specifies a location in the memory array accessed during read operations and write operations. An external address input receives an address value from a device external to the memory device. The received address value may be utilized to randomly access the memory array. An address register/restart address counter is operatively associated with the memory array and the external address input and configured to store a start address for at least a write operation to the memory array, to selectively generate a series of internal addresses to access the memory array based on the stored start address and to selectively return to the stored start address as a start address of a subsequent operation to access the memory array.

Abstract: An apparatus and method for recording a floating point macro instruction error pointer within a microprocessor is provided. The apparatus includes translation/control logic for generating a micro instruction sequence to perform a floating point operation. The micro instruction sequence includes a first micro instruction, inserted in the sequence in place of a translate slip, which directs the microprocessor to store a first part of the floating point macro instruction error pointer associated with a floating point macro instruction. The micro instruction sequence also includes a micro instruction extension, associated with a floating point micro instruction within the sequence. The extension directs the microprocessor to store a second part of the floating point macro instruction error pointer. The error pointer is stored in zero effective time increments without requiring additional hardware.