Abstract: Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and H2SO4 can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm.

Abstract: Embodiments provided herein describe antireflective coatings and methods for forming antireflective coatings. A substrate is provided. A first antireflective layer is formed over the substrate. The first antireflective layer has a first refractive index. A second antireflective layer is formed on the first antireflective layer. The second antireflective layer has a second refractive index. The first antireflective layer and the second antireflective layer jointly form an antireflective coating. The antireflective coating is graded such that the antireflective coating comprises at least three sub-layers, each of the at least three sub-layers having a unique refractive index.

Abstract: MIMCAP diodes are provided that can be suitable for memory device applications, such as current selector devices for cross point memory array. The MIMCAP diodes can have lower thermal budget as compared to Schottky diodes and controllable lower barrier height and lower series resistance as compared to MIMCAP tunneling diodes. The MIMCAP diode can include a barrier height modification layer, a low leakage dielectric layer and a high leakage dielectric layer. The layers can be sandwiched between two electrodes.

Abstract: Provided are superconducting circuits and methods of forming such circuits. A circuit may include a silicon containing low loss dielectric (LLD) layer formed by fluorine passivation of dangling bonds of silicon atoms in the layer. The LLD layer may be formed from silicon nitride or silicon oxide. For uniform passivation (e.g., uniform distribution of fluorine within the LLD layer), fluorine may be introduced while forming the LLD layer. For example, a fluorine containing precursor may be supplied into a deposition chamber together with a silicon containing precursor. Alternatively, the LLD layer may be formed as a stack of many thin sublayers, and each sublayer may be subjected to individual fluorine passivation. For example, low power plasma treatment or annealing in a fluorine containing environment may be used for this purpose. The concentration of fluorine in the LLD layer may be between about 0.5% atomic and 5% atomic.

Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The semiconductor layer of the selector element can include a photo-luminescent or electro-luminescent material. Conductive materials of the MSM may include tungsten, titanium nitride, carbon, or combinations thereof.

Abstract: A co-sputter technique is used to deposit In—Ga—Zn—O films using PVD. The films are deposited in an atmosphere including both oxygen and argon. A heater setpoint of about 300 C results in a substrate temperature of about 165 C. One target includes an alloy of In, Ga, Zn, and O with an atomic ratio of In:Ga:Zn of about 1:1:1. The second target includes a compound of zinc oxide. The films exhibit the c-axis aligned crystalline (CAAC) phase in an as-deposited state, without the need of a subsequent anneal treatment.

Abstract: A nonvolatile resistive memory element includes an oxygen-gettering layer. The oxygen-gettering layer is formed as part of an electrode stack, and is more thermodynamically favorable in gettering oxygen than other layers of the electrode stack. The Gibbs free energy of formation (?fG°) of an oxide of the oxygen-gettering layer is less (i.e., more negative) than the Gibbs free energy of formation of an oxide of the adjacent layers of the electrode stack. The oxygen-gettering layer reacts with oxygen present in the adjacent layers of the electrode stack, thereby preventing this oxygen from diffusing into nearby silicon layers to undesirably increase an SiO2 interfacial layer thickness in the memory element and may alternately be selected to decrease such thickness during subsequent processing.

Abstract: A method is disclosed for the selective etching of a multi-layer metal oxide stack comprising a platinum layer on a TiN layer on an HfO2 or ZrO2 layer on a substrate. In some embodiments, the method comprises a physical sputter process to selectively etch the platinum layer, followed by a plasma etch process comprises CHF3 and oxygen to selectively etch the TiN, HfO2 or ZrO2 layers with respect to the substrate.

Abstract: An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.

Abstract: Two-step process sequences uniformly etch both tungsten-based and titanium-based structures on a substrate. A sequence of wet etches using peroxide and heated nitric acid uniformly recesses a metal stack that includes W, TiN, and TiAl. W, TiN and TiC are uniformly recessed by a peroxide etch at ˜25 C followed by an acid solution with a very small amount of added peroxide at ˜60 C. TiC is etched without etching trench oxides or other metals in a work-function metal stack by either (1) highly-dilute of ultra-dilute HF at 25-35 C, (2) dilute HCl at 25-60 C, (3) dilute NH4OH at 25-60 C, or (4) solution (2) or (3) with small amounts of peroxide. Other metals in the stack may then be plasma-etched without being blocked by TiC residues.

Abstract: A bi-layer seed layer can exhibit good seed property for an infrared reflective layer, together with improved thermal stability. The bi-layer seed layer can include a thin zinc oxide layer having a desired crystallographic orientation for a silver infrared reflective layer disposed on a bottom layer having a desired thermal stability. The thermal stable layer can include aluminum, magnesium, or bismuth doped tin oxide (AlSnO, MgSnO, or BiSnO), which can have better thermal stability than zinc oxide but poorer lattice matching for serving as a seed layer template for silver (111).

Abstract: Provided are superconducting tunnel junctions, such as Josephson tunnel junctions, and a method of fabricating thereof. A junction includes an insulator disposed between two superconductors. The junction may also include one or two interface layers, with each interface layer disposed between the insulator and one of the superconductors. The interface layer is configured to prevent oxygen from entering the adjacent superconductor during fabrication and operation of the junction. Furthermore, the interface layer may protect the insulator from the environment during handling and processing of the junction, thereby allowing vacuum breaks after the interface layer is formed as well as new integration schemes, such as depositing a dielectric layer and forming a trench in the dielectric layer for the second superconductor. In some embodiments, the junction may be annealed during its fabrication to move oxygen from the superconductors and/or from the insulator into the one or two interface layers.

Abstract: In some embodiments, a metal oxide second electrode material is formed as part of a MIM DRAM capacitor stack. The second electrode material is doped with one or more dopants. The dopants may influence the crystallinity, resistivity, and/or work function of the second electrode material. The dopants may be uniformly distributed throughout the second electrode material or may be distributed with a gradient in their concentration profile.

Abstract: Embodiments provided herein describe a low-e panel and a method for forming a low-e panel. A transparent substrate is provided. A metal oxide layer is formed over the transparent substrate. The metal oxide layer includes a first element, a second element, and a third element. A reflective layer is formed over the transparent substrate. The first element may include tin or zinc. The second element and the third element may each include tin, zinc, antimony, silicon, strontium, titanium, niobium, zirconium, magnesium, aluminum, yttrium, lanthanum, hafnium, or bismuth. The metal oxide layer may also include nitrogen.

Abstract: In some embodiments, apparatus are provided that provide for flexible processing in both high productivity combinatorial (HPC) and full wafer modes. The apparatus allow for interchangeable functionality that includes deposition with different sizes of targets, plasma treatment, ion beam treatment, and in-situ metrology. The functional modules are designed so that the modules may be interchanged with minimal effort and reduced system downtime.

Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The semiconductor layer of the selector element can include a silicon carbide/silicon nitride nanolaminate stack. The semiconductor layer of the selector element can include a silicon carbon nitride/silicon nitride nanolaminate stack. Conductive materials of the MSM may include tungsten, titanium nitride, carbon, or a combination thereof.

Abstract: Disclosed herein are systems, methods, and apparatus for forming a low emissivity panel. In various embodiments, a partially fabricated panel may be provided. The partially fabricated panel may include a substrate, a reflective layer formed over the substrate, and a top dielectric layer formed over the reflective layer such that the reflective layer is formed between the substrate and the top dielectric layer. The top dielectric layer may include tin having an oxidation state of +4. An interface layer may be formed over the top dielectric layer. A top diffusion layer may be formed over the interface layer. The top diffusion layer may be formed in a nitrogen plasma environment. The interface layer may substantially prevent nitrogen from the nitrogen plasma environment from reaching the top dielectric layer and changing the oxidation state of tin included in the top dielectric layer.

Abstract: Native oxide growth on germanium, silicon germanium, and InGaAs undesirably affects CET (capacitive equivalent thickness) and EOT (effective oxide thickness) of high-k and low-k metal-oxide layers formed on these semiconductors. Even if pre-existing native oxide is initially removed from the bare semiconductor surface, some metal oxide layers are oxygen-permeable in thicknesses below about 25 ? thick. Oxygen-containing species used in the metal-oxide deposition process may diffuse through these permeable layers, react with the underlying semiconductor, and re-grow the native oxide. To eliminate or mitigate this re-growth, the substrate is exposed to a gas or plasma reductant (e.g., containing hydrogen). The reductant diffuses through the permeable layers to react with the re-grown native oxide, detaching the oxygen and leaving the un-oxidized semiconductor. The reduction product(s) resulting from the reaction may then be removed from the substrate (e.g., driven off by heat).

Abstract: Combinatorial workflow is provided for evaluating materials and processes for current selector devices in a cross point memory array. Blanket layers, metal-insulator-metal devices, and compete memory structures are combinatorially fabricated on multiple regions of a substrate, with each region having a different material and process condition for the current selector devices. The current selector devices are then characterized, and the data are compared to obtain the optimum materials and processes.

Abstract: Transparent conductive layers usable as ohmic contacts for III-V semiconductors with work functions between 4.1 and 4.7 eV are formed by annealing layers of transparent oxide with thin (0.1-5nm) layers of conductive metal. When the layers interdiffuse during the annealing, some of the conductive metal atoms remain free to reduce resistivity and others oxidize to reduce optical absorption. Examples of the transparent oxides include indium-tin oxide, zinc oxide, and aluminum zinc oxide with up to 5 wt % Al. Examples of the metals include aluminum and titanium. The work function of the transparent conductive layer can be tuned to match the contacted semiconductor by adjusting the ratio of metal to transparent oxide.