Abstract: A disc file system is described in which the disc space is divided into very large blocks of at least 64k bytes. A large file is allocated a whole number of these large blocks, contiguously where possible. Small files reside in small file areas each of which is composed of a number of large blocks. Space in these small file areas is allocated in multiples of a small block size (e.g. 4K bytes). The use of large and small blocks reduces the wastage of space that would occur if small files were written into large blocks. The amount of head movement when reading large amounts of data from large files is reduced because of the large block size and because the large blocks are allocated contiguously.

Abstract: A method and apparatus as described for predicting the performance of a computer system. A benchmark program is run on an existing host computer, and is monitored to determine the actual sequence of instructions in the instruction set of the host. These are then converted into the corresponding sequence in the instruction set of the target. The performance of the target system in executing these instructions is then determined.

Abstract: A computer system is described in which users can access a protected resource only by way of a call to a user monitor command, specifying the protected resource as a parameter. The user monitor command checks that certain conditions are satisfied and performs specified actions before permitting access to the protected resource. The checks may include checking whether options and argument values supplied by the user satisfy specified conditions. The actions may include dynamically modifying a supplementary groups list of a current process temporarily granting or removing privileges to or from the user.

Abstract: A distributed computer system, has a number of users and target applications. When a user logs on to the system, an authentication unit issues the user with a privilege attribute certificate (PAC) representing the user's access rights. When the user wishes to access a target application, he presents the PAC to that application as evidence of his access rights. The application, in turn, passes the PAC to a PAC use monitor (PUM) which validates the PAC. The PUM is shared between a plurality of applications.

Abstract: A computer system includes a plurality of programs and a plurality of accessible objects. Each program has an associated program identifier, and at least some of the objects have respective access control lists (ACL). Each ACL entry may comprise a program identifier key and an access permission indication. When a user attempts to access an object by way of a program, an entry in the ACL of the object is selected by matching the entry keys with at least the program identifier of the program, and access is granted or denied on the basis of the access permission indication in the selected entry.

Abstract: A data communications system comprises a number of interconnected nodes. Messages from the nodes are grouped into frames, and the frames are delivered to all the nodes in the same sequence.Whenever a transmission error is detected, all the nodes co-operate to replay the sequence of frames from a particular point which is at least far enough back to ensure retransmission of the earliest frame that could have been in error. Each node then discards all repeated frames that it has already correctly received.

Abstract: A method is described for encoding a first image to produce a second, lower resolution image. For each superpixel group in the first image, a prediction class is formed, based on the values of the pixels in two adjacent superpixels. This prediction class is used to access a table, to obtain a prediction for the corresponding pixel in the second image. If the prediction matches the actual pixel pattern of the superpixel, the corresponding pixel in the second image is set to the predicted colour. If the prediction does not match, then the corresponding pixel in the second image is set to the inverse of the predicted colour, and the actual pixel pattern is stored in a supplementary file. If no prediction is provided, the actual pixel pattern is stored, and the pixel in the second image is set to the colour of the majority of the pixels in the superpixel.

Abstract: A cryptographic services facility uses object-oriented techniques to allow a user to interface with the facility in an algorithm-independent manner. The facility stores algorithm objects which specify algorithm attributes, and context type objects which specify user context attributes such as intended algorithm, intended use, key size and default key. In response to a "create context" request from a user, the context type objects are searched to find a context type that meets the user's requirements, and this is used to create a new context instance. In response to "create context type" requests from the system administrator, a context type factory object searches for an algorithm object that provides a required level of protection and uses this to create a new context type which is then available to users.

Abstract: A data processing system comprises a plurality of processing modules, and a central services module, connected by a system bus. Details of the expected system configuration and of a normal bootstrap load path are held in a non-volatile store. On power-up or system restart, the non volatile store is tested. If the test is satisfactory, a defined bootstrap procedure is executed; otherwise an undefined bootstrap procedure is performed. The defined bootstrap procedure compares the expected configuration with the actual system configuration. If they match, the bootstrap program is loaded from the normal load path. If they do not match, the undefined bootstrap procedure may be entered. In the undefined bootstrap procedure, the central services module searches for possible bootstrap load paths and attempts a load from one of these paths. The defined bootstrap is expected to be the normal procedure, and is faster.

Abstract: A dedicated search processor searches data retrieved from a disc file in response, to search requests from a host processor. The search processor consists of a programmable processor. The processor has a code generator which generates a machine-code search program specifically tailored to the particular combination of search request and data structure, and containing mainly in-line sequences of instructions. The search program can therefore be executed very rapidly, allowing a high search rate to be sustained.

Abstract: A mechanism is described for controlling access to a target application (TA) in a distributed computer system. A user sponsor (US) acting on behalf of an end user is issued with a privilege attribute certificate (PAC) containing initiator qualifier attributes (IQA) identifying permitted users of the PAC. The US obtains a key from a key distribution server (KDS), the key having initiator qualifier attributes of the US cryptographically associated with it.The US uses this key to communicate with the TA, and presents its PAC for verification. If the IQA in the PAC do not match the IQA associated with the key, this indicates that the PAC is being presented by the wrong initiator, and so access is not permitted.If a receiving entity subsequently wishes to act as an initiator and to use the PAC by proxy, it acquires a key from the KDS, the key having the receiving entity's attributes cryptographically associated with it. This provides a way of regulating proxy use of PACs.

Abstract: A data processing unit accesses data in a cache using a virtual address. If the data is not in the cache, the virtual address is translated by a memory management unit (MMU) into a physical address for accessing a main memory. The MMU can also access the cache, using the physical address, to retrieve page table entries held in the cache. This avoids the need for a main memory access to retrieve the page table entries, and hence speeds up the address translation operation. The physically addressed entries in the cache are tagged with a reserved context number to distinguish them from the virtually addressed data.

Abstract: A data processor is provided with a mechanism for controlling its performance. The processor is allowed to run normally for R clock beats, and then further instruction starts are inhibited for W clock beats. The ratio W/R determines the level of performance of the processor.

Abstract: A logic simulator has a time loop with a number of time slots into which events are scheduled. The events are wrapped around the loop, so that event times corresponding to different cycles around the loop may be simultaneously present on the loop. This allows a small loop size to be used, which improves performance. Preferably, the loop size is a prime number. If a complete cycle of the loop is made without finding any non-empty slots a jump is made to the next event time, so as to speed up the processing. In one described embodiment, the loop size is static, while in a second described embodiment the loop size is dynamically varied to minimize the insertion of events with different event times into the same slot.

Abstract: A data processing system consists of a number of processing modules and memory modules interconnected by a common bus. If a memory module is not free to accept addresses or data from the bus, it asserts an address wait (AW) signal or a data wait (DW) signal, as the case may be. When a processing module sends an address or data over the bus, it normally holds it there for one clock cycle only. However, if the relevant wait signal AW or DW is asserted, the address or data is held on the bus until this wait signal is removed. This arrangement avoids the need for acknowledgement on the bus, and hence speeds up the transaction of information.

Abstract: A data processing system comprises a number of processing nodes, each having a processor and a local store. The workload of the system is represented by packets, including function packets specifying a function and pointers to one or more argument packets to which the function is to be applied. When a node processes a function packet, it checks whether all its argument packets are resident in the local store. If not, copies of the argument packets are fetched from the remote nodes in which they reside. These argument packets are referenced by special indirection packets, which contain the local and global address of the argument packet, and a reference count for garbage collection purposes.

Abstract: A data memory system includes a main memory and a copy-back cache. Each line of the cache has a context tag, which is compared with a current context number to test whether the line contains the required data. The cache can be flushed simply by resetting all the context tags to a null value, which ensures that the data cannot be accessed. However, it remains physically in the cache, and will eventually be copied back to the main memory when it is about to be overwritten with different data or when the physical address is next used.

Abstract: A first-in-first-out buffer is described for transferring data between two asynchronous clock regimes. The buffer comprises a first register file, for transferring data from the slow to the fast clock regime, and a second register file for transferring data in the opposite direction. The write addresses for the first register file are produced by a counter in the slow clock regime, and converted back to standard binary, and a predetermined offset is added to the result, so as to produce a read address for the first register file. This is also used as the write address for the second register file. The read address for the second register file is produced by adding a predetermined offset to the output of the counter. Thus, the read and write addresses of the two register files are always in a fixed relationship, so that it is not necessary to provide special logic for detecting the buffer full and buffer empty conditions.

Abstract: A jump prediction circuit predicts the outcome of a conditional jump instruction and is of particular use in a pipelined processor. An initial guess is formed, based on the value of the jump parameter in the instruction. A random-access memory stores the history of the outcome of previously executed jump instructions and is used, when valid, to correct the initial guess to produce a final jump prediction.

Abstract: Data processing apparatus comprises a series of pipeline units each of which consists of a number of pipeline stages. The units are interconnected by a number of parameter files, which provide a number of slots. Whenever an instruction is initiated in the pipeline, it is allocated a slot, and retains that slot until its execution is successfully completed. Two independent streams of instructions are scheduled through the pipeline, each being allocated a fixed number of the slots. In normal operation, one of the streams has priority over the other stream. An instruction is allowed to change the process state only when it successfully terminates at the end of the pipeline, thus ensuring consistency. An instruction can be started in a lower pipeline unit as soon as it is know that its required operand will be available in time from the data slave, thus allowing the operations of these two units to be overlapped.