Patents Assigned to Interuniversitair Microelektronica Centrum
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Publication number: 20130043132Abstract: A device for manipulating magnetic or magnetizable objects in a medium is provided. The device has a surface lying in a plane and comprises a set of at least two conductors electrically isolated from each other, wherein the at least two conductors are adapted for both generating a magnetophoresis force for moving the magnetic or magnetizable objects over the surface of the device in a direction substantially parallel to the plane of the surface, and generating a dielectrophoresis force for moving the magnetic or magnetizable objects in a direction substantially perpendicular to the plane of the surface. Also provided is a method for manipulating magnetic or magnetizable objects in a medium. The method uses a combined magnetophoresis and dielectrophoresis actuation principle for controlling in-plane as well as out-of-plane movement of the magnetic or magnetizable objects.Type: ApplicationFiled: August 23, 2007Publication date: February 21, 2013Applicants: Katholieke Universiteit Leuven, Interuniversitair Microelektronica Centrum (IMEC)Inventors: Chengxun Liu, Liesbet Lagae
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Patent number: 8373236Abstract: The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (1) comprising a bipolar transistor with in that order a collector region (2), a base region (3), and an emitter region (4), wherein the semiconductor body comprises a projecting mesa (5) comprising at least a portion of the collector region (2) and the base region (3), which mesa is surrounded by an isolation region (6). According to the invention, the semiconductor device (10) also comprises a field effect transistor with a source region, a drain region, an interposed channel region, a superimposed gate dielectric (7), and a gate region (8), which gate region (8) forms a highest part of the field effect transistor, and the height of the mesa (5) is greater than the height of the gate region (8). This device can be manufactured inexpensively and easily by a method according to the invention, and the bipolar transistor can have excellent high-frequency characteristics.Type: GrantFiled: June 12, 2007Date of Patent: February 12, 2013Assignees: NXP, B.V., Interuniversitair Microelektronica Centrum VZWInventors: Erwin Hijzen, Joost Melai, Wibo Van Noort, Johannes Donkers, Philippe Meunier-Beillard, Andreas M. Piontek, Li Jen Choi, Stefaan Van Huylenbroeck
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Publication number: 20120279837Abstract: An electrostatically actuatable micro electromechanical device is provided with enhanced reliability and lifetime. The electrostatically actuatable micro electromechanical device comprises: a substrate, a first conductor fixed to the top layer of the substrate, forming a fixed electrode, a second conductor fixed to the top layer of the substrate, and a substrate area. The second conductor is electrically isolated from the first conductor and comprises a moveable portion, suspended at a predetermined distance above the first conductor, the moveable portion forming a moveable electrode which approaches the fixed electrode upon applying an actuation voltage between the first and second conductors. The selected substrate surface area is defined as the orthogonal projection of the moveable portion on the substrate between the first and second conductors. In the substrate surface area at least one recess is provided in at least the top layer of the substrate.Type: ApplicationFiled: March 31, 2009Publication date: November 8, 2012Applicants: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Ingrid De Wolf, Xavier Rottenberg, Piotr Czarnecki, Philippe Soussan
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Publication number: 20120069645Abstract: A phase change memory cell has more than one memory region (14,18) each being a narrowed region of phase change memory material (2) extending between first and second electrodes (4,6). Each of the plurality of memory regions (14, 18) can be programmed to be in a low resistance state or a high resistance state by applying suitable programming conditions of current and/or voltage. The resistances of the high resistance states and the programming conditions to convert the high resistance states to the low resistance state are different in each of the plurality of memory regions.Type: ApplicationFiled: March 30, 2009Publication date: March 22, 2012Applicants: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW, NXP B.V.Inventors: Ludovic R.A. Goux, Thomas Gille, Judit G. Lisoni, Dirk J.C.C.M. Wouters
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Publication number: 20120034787Abstract: The present invention provides an etching solution for revealing defects in a germanium layer, a method for revealing defects in a germanium layer using such an etching solution and to a method for making such an etching solution. The etching solution according to embodiments of the present invention is able to exhibit an etch rate of between 4 nm·min?1 and 450 nm·min?1, which makes it suitable to be used for revealing defects in a thin layer of germanium, i.e. in a layer of germanium with a thickness of between 20 nm and 10 ?m, for example between 20 nm and 2 ?m, between 20 nm and 1 ?m or between 20 nm and 200 nm.Type: ApplicationFiled: October 18, 2011Publication date: February 9, 2012Applicant: Interuniversitair Microelektronica Centrum vzw (IMEC)Inventors: Laurent Souriau, Valentina Terzieva
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Publication number: 20120018696Abstract: A vertical phase change memory cell (2) has an active region (24) of phase change memory material defined either by providing a contact extending only over part of the phase change memory material or an insulating layer exposing only part of the phase change memory material. There may be more than one active region (24) per cell allowing more than one bit of data to be stored in each cell.Type: ApplicationFiled: March 30, 2009Publication date: January 26, 2012Applicants: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW, NXP B.V.Inventor: Ludovic R. A. Goux
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Publication number: 20110311227Abstract: Systems and methods for transferring incoming single-ended burst signals of which at least one characteristic varies widely from burst to burst onto a pair of differential lines. The systems comprise an input for receiving an incoming burst signal, a signal adaptation block for adapting said widely varying characteristic and a single-ended-to-differential converter. In a first aspect a reset signal for resetting a settings determination block, which controls the signal adaptation block, is sent backwards over the differential lines, preferably using a common-mode signal. In a second aspect, a status freezing mechanism is employed for freezing the settings of the settings determination block after the end of the preamble of an incoming burst.Type: ApplicationFiled: April 4, 2008Publication date: December 22, 2011Applicants: Universiteit Gent, Interuniversitair Microelektronica Centrum (IMEC)Inventors: Peter Ossieur, Tine De Ridder, Johan Bauwelinck, Xing Zhi Qiu, Jan Vandewege
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Publication number: 20110309457Abstract: Methods of providing a semiconductor device with a control electrode structure having a controlled overlap between control electrode and first and second main electrode extensions without many spacers are disclosed. A preferred method provides a step of etching back an insulating layer performed after amorphizing and implanting the main electrode extensions. Preferably, the step that amorphizes the extensions also partly amorphizes the insulating layer. Because etch rates of amorphous insulator and crystalline insulator differ, the amorphized portion of the insulating layer may serve as a natural etch stop to enable even better fine-tuning of the overlap. Corresponding semiconductor devices are also provided.Type: ApplicationFiled: June 23, 2011Publication date: December 22, 2011Applicants: Koninkiijke Philips Electronics N.V., Interuniversitair Microelektronica centrum (IMEC)Inventors: Kirklen Henson, Radu Catalin Surdeanu
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Publication number: 20110230172Abstract: Presented is a method of managing the operation of a system including a processing subsystem configured to run a multimedia application and a telecommunication subsystem. The method includes determining telecom environment conditions, and selecting a working point from a plurality of predetermined working points. The selecting is based at least in part on the determined environmental conditions. The method also includes setting control parameters in the multimedia application and/or the telecommunication subsystem to configure the system to operate at the selected working point, and operating the system at the selected working point.Type: ApplicationFiled: February 17, 2011Publication date: September 22, 2011Applicant: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Sofie Pollin, Bruno Bougard, Gregory Lenoir, Francky Catthoor
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Patent number: 8020163Abstract: Network on Chip (NoC) Devices, especially Heterogeneous Multiprocessor Network on Chip Devices are described, that optionally contain Reconfigurable Hardware Tiles, as well as Methods and Operating Systems (OS) for Control thereof. In accordance with an aspect of the present invention the Operating Systems handle either (a) run-time traffic management methods or (b) task migration methods, or a combination of these methods. The Operating Systems may be partly distributed but with a centralized master. The traffic management methods and apparatus of the invention use a statistical QoS approach. A system is described having an at least dual Network on Chip as well as methods of operating the same. The system has at least an on-chip communications network, comprising a first on-chip data traffic network (data NoC) and a second on-chip control traffic network (control NoC), having a control network interface component (control NIC) and a data network interface component (data NIC).Type: GrantFiled: November 24, 2004Date of Patent: September 13, 2011Assignees: Interuniversitair Microelektronica Centrum (IMEC), Xilinx, Inc.Inventors: Vincent Nollet, Paul Coene, Theodore Marescaux, Prabhat Avasare, Jean-Yves Mignolet, Serge Vernalde, Diederik Verkest
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Publication number: 20110198671Abstract: The invention relates to a semiconductor device (30) comprising a substrate (1), a semiconductor body (25) comprising a bipolar transistor that comprises a collector region (3), a base region (4), and an emitter region (15), wherein at least a portion of the collector region (3) is surrounded by a first isolation region (2, 8), the semiconductor body (25) further comprises an extrinsic base region (35) arranged in contacting manner to the base region (4). In this way, a fast semiconductor device with reduced impact of parasitic components is obtained.Type: ApplicationFiled: August 5, 2009Publication date: August 18, 2011Applicants: NXP B.V., INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZWInventors: Guillaume Boccardi, Mark C. J. C. M. Kramer, Johannes J. T. M. Donkers, Li Jen Choi, Stefaan Decoutere, Arturo Sibaja-Hernandez, Stefaan Van Huylenbroeck, Rafael Venegas
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Publication number: 20110183509Abstract: A non-volatile memory device having a control gate on top of the second dielectric (interpoly or blocking dielectric), at least a bottom layer of the control gate in contact with the second dielectric being constructed in a material having a predefined high work-function and showing a tendency to reduce its work-function when in contact with a group of certain high-k materials after full device fabrication. At least a top layer of the second dielectric, separating the bottom layer of the control gate from the rest of the second dielectric, is constructed in a predetermined high-k material, chosen outside the group for avoiding a reduction in the work-function of the material of the bottom layer of the control gate. In the manufacturing method, the top layer is created in the second dielectric before applying the control gate.Type: ApplicationFiled: April 5, 2011Publication date: July 28, 2011Applicants: Interuniversitair Microelektronica Centrum vzw (IMEC), Samsung Electronics Co. Ltd.Inventors: Bogdan Govoreanu, HongYu Yu, Hag-Ju Cho
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Publication number: 20110080781Abstract: The present invention relates to a phase change memory device comprising a plurality of phase change memory cells, each cell comprising a phase change material (50) conductively coupled between a first electrode (44) and a second electrode (42) for applying a reset current pulse having a predefined polarity to the phase change material in a programming cycle of the phase change memory device; and a controller (70) coupled to the first electrode and the second electrode for reversing the polarity of the reset current pulse to be applied in a next number of programming cycles to the corresponding cell after the application of a first number of programming cycles to the corresponding cell. The present invention further relates to a method for controlling such a memory device.Type: ApplicationFiled: June 9, 2009Publication date: April 7, 2011Applicants: NXP B.V., INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZWInventor: Ludovic Goux
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Publication number: 20110049634Abstract: A method of manufacturing a semiconductor device having gate electrodes of a suitable work function material is disclosed. The method comprises providing a substrate (100) including a number of active regions (110, 120) and a dielectric layer (130) covering the active regions (110, 120), and forming a stack of layers (140, 150, 160) over the dielectric layer. The formation of the stack of layers comprises depositing a first metal layer (140), having a first thickness, e.g.Type: ApplicationFiled: March 30, 2009Publication date: March 3, 2011Applicants: NXP B.V., INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZWInventors: Raghunath Singanamalla, Jacob C. Hooker, Marcus J. H. Van Dal
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Publication number: 20110026921Abstract: Systems and methods for transferring incoming single-ended burst signals of which at least one characteristic varies widely from burst to burst onto a pair of differential lines. The systems comprise an input for receiving an incoming burst signal, a signal adaptation block for adapting said widely varying characteristic and a single-ended-to-differential converter. In a first aspect a reset signal for resetting a settings determination block, which controls the signal adaptation block, is sent backwards over the differential lines, preferably using a common-mode signal. In a second aspect, a status freezing mechanism is employed for freezing the settings of the settings determination block after the end of the preamble of an incoming burst.Type: ApplicationFiled: April 4, 2008Publication date: February 3, 2011Applicants: Interuniversitair Microelektronica Centrum (IMEC), Universiteit GentInventors: Peter Ossieur, Tine De Ridder, Johan Bauwelinck, Xing Zhi Qiu, Jan Vandewege
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Publication number: 20100285656Abstract: The present invention relates to a method for forming metal-silicide catalyst nanoparticles with controllable diameter. The method according to embodiments of the invention leads to the formation of ‘active’ metal-suicide catalyst nanoparticles, with which is meant that they are suitable to be used as a catalyst in carbon nanotube growth. The nano-particles are formed on the surface of a substrate or in case the substrate is a porous substrate within the surface of the inner pores of a substrate. The metal-silicide nanoparticles can be Co-silicide, Ni-silicide or Fe-silicide particles. The present invention relates also to a method to form carbon nanotubes (CNT) on metal-silicide nanoparticles, the metal-silicide containing particles hereby acting as catalyst during the growth process, e.g. during the chemical vapour deposition (CVD) process. Starting from very defined metal-containing nanoparticles as catalysts, the diameter of grown CNT can be well controlled and a homogeneous set of CNT will be obtained.Type: ApplicationFiled: June 16, 2006Publication date: November 11, 2010Applicant: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Santiago Cruz Esconjauregui, Caroline Whelan, Karen Maex
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Patent number: 7831951Abstract: A system and method of designing digital system. One aspect of the invention includes a method for designing an essentially digital system, wherein Pareto-based task concurrency optimization is performed. The method uses a system-level description of the functionality and timing of the digital system. The system-level description comprises a plurality of tasks. Task concurrency optimization is performed on said system-level description, thereby obtaining a task concurrency optimized system-level description, including Pareto-like task optimization information. The essentially digital system is designed based on said task concurrency optimized system-level description. In one embodiment of the invention, the description is includes a “grey-box” description of the essentially digital system.Type: GrantFiled: June 11, 2007Date of Patent: November 9, 2010Assignees: Interuniversitair Microelektronica Centrum (IMEC), Katholieke Universiteit Leuven, University of PatrasInventors: Francky Catthoor, Peng Yang, Chun Wong, Paul Marchal, Aggeliki Prayati, Nathalie Cossement, Rudy Lauwereins
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Publication number: 20100225369Abstract: The disclosure relates to a device comprising at least one delay line for applying a variable delay to a clock signal and a controller for controlling the variable delay of the delay line. Each delay line comprises a plurality of concatenated delay banks which provide different delay values with respect to each other, a bypass parallel over each of said the delay banks, and switching elements associated with each of the delay banks for selecting either the respective delay bank or the respective bypass. Each of the delay banks is provided with a delay bank status indicator for indicating propagation of the clock signal through the delay bank towards the controller. The controller is provided for taking the indicated propagation of the clock signal into account upon setting said switching elements.Type: ApplicationFiled: February 2, 2007Publication date: September 9, 2010Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC)Inventor: Mustafa Badaroglu
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Publication number: 20100164487Abstract: The present invention relates to a device and corresponding method for ultrafast controlling of the magnetization of a magnetic element. A device (100) includes a surface acoustic wave generating means (102), a transport layer (104), which is typically functionally and partially structurally comprised in said SAW generating means (102), and at least one ferromagnetic element (106). A surface acoustic wave is generated and propagates in a transport layer (104) which typically consists of a piezo-electric material. Thus, strain is induced in the transport layer (104) and in the ferromagnetic element (106) in contact with this transport layer (104). Due to magneto elastic coupling this generates an effective magnetic field in the ferromagnetic element (106). If the surface acoustic wave has a frequency substantially close to the ferromagnetic resonance (FMR) frequency ?FMR the ferromagnetic element (106) is absorbed well and the magnetization state of the element can be controlled with this FMR frequency.Type: ApplicationFiled: December 29, 2009Publication date: July 1, 2010Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC)Inventors: Wouter Eyckmans, Liesbet Lagae
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Publication number: 20100127233Abstract: The present disclosure provides a method for controlled formation of the resistive switching layer in a resistive switching device. The method comprises providing a substrate (2) comprising the bottom electrode (10), providing on the substrate a dielectric layer (4) comprising a recess (7) containing the metal for forming the resistive layer (11), providing on the substrate a dielectric layer (5) comprising an opening (8) exposing the metal of the recess, and forming the resistive layer in the recess and in the opening.Type: ApplicationFiled: August 31, 2007Publication date: May 27, 2010Applicants: NXP, B.V., INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC)Inventors: Ludovic Goux, Dirk Wouters