Abstract: A switched delay section for an integrated circuit device is disclosed. The switched delay section includes a segmented inductor loop comprising a plurality of segments separated by nodes. A plurality of capacitors are coupled between the segmented inductor loop to provide a plurality of delay sections. An image loop is in electrical communication with the segmented inductor loop. The image loop includes a switch configured to place the plurality of capacitors in one of a high capacitance or a low capacitance state to provide a variable delay value.

Abstract: This frequency tripler system uses a cascade of integrated transistor circuit differential limiting amplifiers and tunable notch filters that can directly serve one or more outputs, such as a direct clock or local oscillator drive. With this topology, filtering is distributed between two or more stages of differential limiting amplifiers and tunable notch filters. This enables suppression of smaller fundamental tone by the differential limiting amplifiers along with the tunable notch filters and yields a strong third harmonic signal to directly drive high performance mixers and digital-to-analog converters.

Abstract: A power conveyor circuit for an energy harvesting system includes an input port configured to be electrically coupled to a sensor to receive an input signal from the sensor at an input power level and an output port configured to 5 be electrically coupled to a load. A switch mode power path circuit is coupled to the input port and the output port to receive the input signal from the sensor received at the input port and to provide an output signal to the output port at an output power level equal to the input power level times a transfer efficiency. A method of making the power conveyor circuit and an energy harvesting system including the power conveyor circuit are also disclosed.

Abstract: An integrated amplifier device includes a main amplifier configured to be coupled to an input source. A replica amplifier is coupled to the main amplifier to provide a bias to the main amplifier. A transconductance biasing cell to the main amplifier and the replica amplifier. The transconductance biasing cell is configured to bias both the main amplifier and the replica amplifier. A method of making an integrated amplifier device is also disclosed.

Abstract: An integrated amplifier device includes a main amplifier configured to be coupled to an input source. A replica amplifier is coupled to the main amplifier to provide a bias to the main amplifier. A transconductance biasing cell to the main amplifier and the replica amplifier. The transconductance biasing cell is configured to bias both the main amplifier and the replica amplifier. A method of making an integrated amplifier device is also disclosed.

Abstract: A self-starting bandgap reference circuit comprises a bias current source configured to provide a bias current. A bandgap core coupled to the bias current source includes a first device configured to receive the bias current and provide a first current output based on the bias current and a second device configured to receive the bias current and provide a second current output based on the bias current. A difference mirror coupled to the first device and the second device receives the first current output and the second current output and is configured to provide a difference current between the second current output and the first current output that is a proportional-to-absolute temperature current. A voltage reference output and a current reference output coupled to the difference mirror receives the proportional-to-absolute temperature current and provides a voltage reference and a current reference based on the proportional-to-absolute temperature current.

Abstract: An analog to digital converter includes an error integration circuit configured to receive an input charge from a detector and to integrate a difference between the input charge and one or more feedback charge pulses to create an error voltage. A quantizer is in operable communication with the error integration circuit and is responsive to the created error voltage. An accumulator having a mantissa component and a radix component is in operable communication with the quantizer. A charge feedback device in operable communication with the quantizer and the radix component of the accumulator. The charge feedback device is configured to generate the one or more feedback charge pulses proportional to the radix component of the accumulator and an output of the quantizer. Digital focal plane read out integrated circuits including the analog to digital converter are also disclosed.

Abstract: A photodiode architecture comprises first, second, and third independent photodiodes, and a shared electrode. The first, second, and third photodiodes are each connected to respective sources of bias voltage and to a common shared electrode, whereby the photodiode architecture comprises at least one of a shared anode and shared cathode photodiode architecture. The photodiode architecture selectively reverse biases the first, second, and third photodiodes so that, during operation, at least one of the first, second and third photodiodes is always operating in a photoconducting mode, to enable capture and storage of charge from any photodiode in the architecture operating in photoconducting mode. Advantageously, the first photodiode can be configured to respond to a first wavelength of light and at least one of the second and third is photodiodes can be configured to be responsive to a respective second or third wavelength of light shorter than the first wavelength of light.

Abstract: A programmable Sigma-Delta Modulator (SDM) includes a first input to select an oversampling rate (OSR), which has a corresponding resonator coefficient value to provide an optimal notch in the Noise Transfer Function (NTF).