Abstract: An electronic memory using true and complementary dual bit lines and dual binary storage elements cell architecture comprising a memory cell pair with four binary storage elements with each memory cell pair capable of existing in up to sixteen electronic memory states. The four binary storage elements together, normally used to store two true and complementary data bits, are used to store two, three, or four data bits depending on the noise margin allowed and bit width selection. The memory can be ferroelectric memory FeRAM, a flash memory, a ROM, a dynamic memory DRAM, an OUM, a MRAM, a NAND memory, or a NOR memory.

Abstract: A method of designing an integrated circuit to be Single Event Upset (SEU) immune by converting one or more Single Event Transient (SET) sensitive transistors into at least two serially connected transistors, and spacing the transistors sufficiently far apart so that the probability of a specified high-energy particle striking both transistors at the same time is remote.

Abstract: An electronic memory using true and complementary dual bit lines and dual binary storage elements cell architecture comprising a memory cell pair with four binary storage elements with each memory cell pair capable of existing in up to sixteen electronic memory states. The four binary storage elements together, normally used to store two true and complementary data bits, are used to store two, three, or four data bits depending on the noise margin allowed and bit width selection. The memory can be ferroelectric memory FeRAM, a flash memory, a ROM, a dynamic memory DRAM, an OUM, a MRAM, a NAND memory, or a NOR memory.

Abstract: An electronic memory comprising a memory cell pair with each memory cell capable of existing in three or more electronic memory states so that the pair is capable of existing in nine electronic states. The memory cell is capable of storing three data bits plus an extra state that can be used for data integrity. The memory can be a flash memory, an ROM, a dynamic memory, an OUM, an MRAM, an NAND memory or an NOR memory.

Abstract: A ferroelectric memory including a bit line pair, a drive line parallel to and located between the bit lines, and an associated memory cell. The memory cell includes two capacitors, each capacitor connected to one of said bit lines via a transistor, and each capacitor is also connected to the drive line via a transistor. The gates of all three of the transistors are connected to a word line perpendicular to the bit lines and drive line, so that when the word line is not selected, the capacitors are completely isolated from any disturb. The bit lines may be complementary and the cell a one-bit cell, or the cell may be a two-bit cell. In the latter case, the memory includes a dummy cell identical to the above cell, in which the two dummy capacitors are complementary. A sense amplifier with three bit line inputs compares the cell bit line with a signal derived from the two dummy bit lines. The logic states of the dummy capacitors alternate in each cycle, preventing imprint and fatigue.