Abstract: A method for identifying log likelihood ratio (LLR) values includes programming codewords into nonvolatile memory devices in response to receiving host-requested write instructions and performing background reads of the programmed codewords in a block at a default threshold voltage, at one or more threshold voltage offset that is less than the default threshold voltage and at one or more threshold voltage offset that is greater than the default threshold voltage. One of the background reads is decoded to identify the stored codeword(s) and a set of LLR values is identified using the stored read results and the identified codeword(s). The process of performing background reads, storing, decoding and identifying is repeated to identify a set of LLR values for each block and further to identify updated sets of LLR values. Host-requested reads are performed and are decoded using LLR values from the updated set of LLR values corresponding to the block that was read.

Abstract: A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. The nonvolatile memory system includes a read circuit that performs background reads of an indicator page of each block to identify outlier blocks. A background reference positioning circuit performs background reads of representative pages of the outlier block at threshold voltage offsets to identify sets of updated threshold voltage offset values. Upon endurance events, retention timer events and read disturb events at a closed block background reads are performed of representative pages of the closed block at threshold voltage offsets to identify sets of updated threshold voltage offset values.

Abstract: A transparent clock converter is interposed between a non-precision time protocol (non-PTP) enabled network node and other portions of the network. The transparent clock converter effectively converts the non-PTP node into a transparent clock node. In some embodiments the transparent clock converter includes physical layer devices, but not media access controllers.

Abstract: A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. Upon the occurrence of one or more of an endurance event, a retention timer event and a read disturb event at a closed block, a background reference positioning circuit performs background reads of representative pages of each page group of a closed block at offsets to each threshold voltage that is required for reading the representative pages of each page group of the closed block to identify a set of updated threshold voltage offset values for each page group of the closed block. When a usage characteristic is determined to meet a usage characteristic threshold, a read circuit performs subsequent host-requested reads using a threshold voltage shift read instruction and reads of pages of the closed block are performed using the set of updated threshold voltage offset values corresponding to the page group of the page being read.

Abstract: A nonvolatile memory controller and a method for erase suspend management are disclosed. The nonvolatile memory controller includes an erase suspend circuit configured for determining a pre-suspend time each time that an erase operation of the nonvolatile memory device is suspended and for determining whether an erase-suspend limit has been reached using the determined pre-suspend time. The erase suspend circuit is further configured for incrementing the number of program and erase cycles when the erase-suspend limit has been reached.

Abstract: A nonvolatile memory controller and a method for erase suspend management are disclosed. The nonvolatile memory controller includes an erase suspend circuit configured for determining a pre-suspend time each time that an erase operation of the nonvolatile memory device is suspended and for determining whether an erase-suspend limit has been reached using the determined pre-suspend time. The erase suspend circuit is further configured for incrementing the number of program and erase cycles when the erase-suspend limit has been reached.

Abstract: A Solid State Drive (SSD) that includes a host connector receptacle for connecting to a host computer, a plurality of NAND devices and a nonvolatile memory controller. The nonvolatile memory controller is configured to perform program operations and read operations on memory cells of each of the NAND devices. The nonvolatile memory controller includes a program step circuit configured to initially program memory cells of each of the NAND devices using an initial program step voltage and is configured to change the program step voltage used to program the memory cells of each of the NAND devices during the lifetime of each of the NAND devices.

Abstract: A nonvolatile memory controller is disclosed that includes a read circuit configured to read memory cells of a nonvolatile memory device and a program and erase circuit configured to program and erase memory cells of the nonvolatile memory device. The nonvolatile memory controller includes a NAND shared algorithm circuit configured to communicate with the nonvolatile memory device so as to enter a test mode of the nonvolatile memory device and configured to modify the trim registers while the nonvolatile memory device is in the test mode such that the nonvolatile memory device performs one or more operations. The operations may include a suspendable program operation, a program suspend operation and an erase suspend operation.

Abstract: A nonvolatile memory controller and a method for erase suspend management are disclosed. The nonvolatile memory controller includes an erase suspend circuit configured for determining a pre-suspend time each time that an erase operation of the nonvolatile memory device is suspended and for determining whether an erase-suspend limit has been reached using the determined pre-suspend time. The erase suspend circuit is further configured for preventing subsequent suspends of the erase operation when the erase-suspend limit has been reached.

Abstract: A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. The nonvolatile memory system includes a read circuit that performs background reads of an indicator page of each block to identify outlier blocks. A background reference positioning circuit performs background reads of representative pages of the outlier block at threshold voltage offsets to identify sets of updated threshold voltage offset values. Upon endurance events, retention timer events and read disturb events at a closed block background reads are performed of representative pages of the closed block at threshold voltage offsets to identify sets of updated threshold voltage offset values.

Abstract: A method for identifying log likelihood ratio (LLR) values includes programming codewords into nonvolatile memory devices in response to receiving host-requested write instructions and performing background reads of the programmed codewords in a block at a default threshold voltage, at one or more threshold voltage offset that is less than the default threshold voltage and at one or more threshold voltage offset that is greater than the default threshold voltage. One of the background reads is decoded to identify the stored codeword(s) and a set of LLR values is identified using the stored read results and the identified codeword(s). The process of performing background reads, storing, decoding and identifying is repeated to identify a set of LLR values for each block and further to identify updated sets of LLR values. Host-requested reads are performed and are decoded using LLR values from the updated set of LLR values corresponding to the block that was read.

Abstract: A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. Upon the occurrence of one or more of an endurance event, a retention timer event and a read disturb event at a closed block, a background reference positioning circuit performs background reads of representative pages of each page group of a closed block at offsets to each threshold voltage that is required for reading the representative pages of each page group of the closed block to identify a set of updated threshold voltage offset values for each page group of the closed block. When a usage characteristic is determined to meet a usage characteristic threshold, a read circuit performs subsequent host-requested reads using a threshold voltage shift read instruction and reads of pages of the closed block are performed using the set of updated threshold voltage offset values corresponding to the page group of the page being read.

Abstract: A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. The nonvolatile memory controller includes a storage module configured to store data indicating threshold voltage shift read parameters and corresponding index values. The nonvolatile memory controller includes a status circuit configured to determine at least one usage characteristic of a nonvolatile memory device, and a read circuit configured to determine whether a usage characteristic meets a usage characteristic threshold. When a usage characteristic is determined to meet the usage characteristic threshold, the read circuit is configured to perform all subsequent reads of the nonvolatile memory device using a threshold voltage shift read instruction identified using one or more of the threshold voltage shift read parameters.