Patents Assigned to IQ-Analog Corporation
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Patent number: 9007108Abstract: A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.Type: GrantFiled: December 8, 2014Date of Patent: April 14, 2015Assignee: IQ-Analog CorporationInventors: Mikko Waltari, Michael Kappes, William Huff
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Patent number: 8928513Abstract: A current steering digital-to-analog converter (DAC) switch driver circuit is provided. The circuit is composed of a conditioning module having a signal input to accept a binary logic digital signal, and signal outputs to supply differential driver signals V+ and V? with a low voltage level (Vlow) greater than the binary logic digital signal low voltage level. Typically, Vlow has a greater potential than ground (0V). A DAC current steering cell has a signal input to accept the differential driver signals and an output to supply a differential analog current responsive to the differential driver signals. The DAC current steering cell may be an NMOS DAC current steering cell. The conditioning module may be a CMOS switch driver, or composed of a level shifter followed by a CMOS switch driver.Type: GrantFiled: September 18, 2014Date of Patent: January 6, 2015Assignee: IQ-Analog CorporationInventor: Mikko Waltari
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Patent number: 8917125Abstract: A system and method are provided of performing background corrections for an interleaving analog-to-digital converter (ADC). An analog input signal s1(t) is accepted having a first frequency f1 and a bandwidth (BW). The method generates a clock at frequency fs, and creates 2 sample clocks with evenly spaced phases, each having a sample clock frequency of fs/2. The method also generates a first tone signal s2(t) having a predetermined second frequency f2 outside BW. The analog input signal and the first tone signal are combined, creating a combination signal, which is sampled using the sample clocks, creating 2 digital sample signals per clock period 1/fs. The 2 digital sample signals are interleaved, creating an interleaved signal. Corrections are applied that minimize errors in the interleaved signal, to obtain a corrected digital output. Errors are determined at an alias frequency f3, associated with the second frequency f2, to obtain correction information.Type: GrantFiled: October 10, 2014Date of Patent: December 23, 2014Assignee: IQ-Analog CorporationInventor: Mikko Waltari
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Patent number: 8917124Abstract: A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.Type: GrantFiled: October 1, 2014Date of Patent: December 23, 2014Assignee: IQ-Analog CorporationInventors: Mikko Waltari, Michael Kappes, William Huff
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Patent number: 8878577Abstract: A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.Type: GrantFiled: November 15, 2013Date of Patent: November 4, 2014Assignee: IQ-Analog CorporationInventors: Mikko Waltari, Michael Kappes, William Huff
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Patent number: 8760335Abstract: A data converter module is provided with an analog interface to receive analog signals, a digital interface to transmit digital signals, and a configuration interface to accept configuration signals. The data conversion module also includes a data conversion array (DCA) with selectively engageable data conversion circuits for the conversion of analog input signals to digital output signals, where the data conversion circuits are responsive to the configuration signals. The DCA's data conversion circuits include configurable data resolution circuits and configurable data conversion speed circuits. For example, the configurable data resolution circuits may be selected from averaging, oversampling, and multi-stage pipelining circuits. The DCA configurable data speed circuit may interleave the outputs from multiple parallelly connected ADCs operating at different clock phases. In one aspect, the number of clock phases is selectable. Also provided are methods for configurable data conversion.Type: GrantFiled: January 27, 2014Date of Patent: June 24, 2014Assignee: IQ-Analog CorporationInventor: Michael Kappes
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Patent number: 8711026Abstract: A data converter module is provided with an analog interface to receive analog signals, a digital interface to transmit digital signals, and a configuration interface to accept configuration signals. The data conversion module also includes a data conversion array (DCA) with selectively engageable data conversion circuits for the conversion of analog input signals to digital output signals, where the data conversion circuits are responsive to the configuration signals. The DCA's data conversion circuits include configurable data resolution circuits and configurable data conversion speed circuits. For example, the configurable data resolution circuits may be selected from averaging, oversampling, and multi-stage pipelining circuits. The DCA configurable data speed circuit may interleave the outputs from multiple parallelly connected ADCs operating at different clock phases. In one aspect, the number of clock phases is selectable. Also provided are methods for configurable data conversion.Type: GrantFiled: October 10, 2013Date of Patent: April 29, 2014Assignee: IQ-Analog CorporationInventor: Michael Kappes
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Publication number: 20140070859Abstract: A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.Type: ApplicationFiled: November 15, 2013Publication date: March 13, 2014Applicant: IQ-Analog CorporationInventors: Mikko Waltari, Michael Kappes, William Huff