Abstract: A charge detection system used in an image sensor consists of the vertical punch through transistor with the gate surrounding its source and connected to it. The charge detector has a large conversion gain, high dynamic range, low reset feed through, and low noise. It senses charge nondestructively, which avoids generation of kTC noise. Additional embodiments of the invention include a standard reset gate option, a resistive reset gate option, and a lateral punch through transistor reset option to minimize the reset feed through. The charge detection system can be used in all know CCD image sensor architectures as well as in most CMOS image sensor architectures.

Abstract: A Dual Gate BCMD pixel has a compact size, nondestructive readout; complete reset with no kTC-reset noise generation, anti-blooming protection, and column reset capability. By incorporating a dual gate MOS transistor with an enclosed annular layout into the pixels of image sensing array, and sensing photo-generated charge nondestructively by detecting the transistor threshold voltage variations caused by collected charge, achieves this goal and other objects of the invention.

Abstract: Generally, and in one form of the invention, a monolithic solid state image-sensing device is disclosed. The device utilizes only a single layer of polysilicon deposition in its fabrication process that is split into two or more phases by very narrow gaps. The single polysilicon layer makes the fabrication process simpler and more compatible with modern semiconductor manufacturing technology. The device also incorporates a lateral anti-blooming drain structure that is formed by a self-aligned diffusion process and does not need a polysilicon gate for its proper function.

Abstract: In an image sensing array, the structure of the image sensor pixel is based on a vertical punch through transistor with a junction gate surrounding its source and connected to it, the junction gate being further surrounded by an MOS gate. The new pixel has a large conversion gain, high dynamic range, blooming protection, and low dark current. It senses charge nondestructively with a complete charge removal, which avoids generation of kTC noise. The pixel fabrication is compatible with CMOS processing that includes two metal layers. The array also includes the pixel reset through column sense lines, polysilicon field plate in the image-sensing area for improved pixel isolation, denser pixel packing, and either n-channel or p-channel addressing transistor.

Abstract: A new High Dynamic Range charge detection concept useful for CCD and Active Pixel CMOS image sensors uses at least one transistor operating in a punch through mode for the charge detection node reset. The punch through operation significantly reduces the reset feed through which leads to a higher voltage swing available on the node for the signal. This in turn allows building smaller and thus more sensitive charge detection nodes. The undesirabe artifacts, associated with the incomplete reset that are induced by the punch through operation, are completely removed by incorporating the CDS signal processing method into the signal processing chain. The incomplete reset artifact removal by the CDS technique is extended to all other resetting concepts that are modeled by a large reset time constant. The punch through concept is suitable for resetting Floating Diffusion charge detection nodes as well as Floating Gate charge detection nodes.

Abstract: Generally, and in one form of the invention, a monolithic solid state image-sensing device is disclosed. The device utilizes only a single layer of polysilicon deposition in its fabrication process that is split into two or more phases by very narrow gaps. The single polysilicon layer makes the fabrication process simpler and more compatible with modern semiconductor manufacturing technology. The device also incorporates a lateral anti-blooming drain structure that is formed by a self-aligned diffusion process and does not need a polysilicon gate for its proper function.

Abstract: A charge carrier multiplier is disclosed in which a carrier that passes through a high-field region lying entirely within the depleted semiconductor volume causes a single-step impact ionization without avalanching. By spacing the high-field region sufficiently away from any substrate region that is not depleted of carriers of opposite polarity than the ionizing carrier, generation of unwanted spurious charge is minimized. Preferably the cell includes a depleted channel formed in a substrate, a gate structure insulatively disposed over and transverse to the channel having an aperture formed therein, and a charge multiplication gate electrode insulatively disposed over the aperture. In one embodiment, the gate electrode structure includes a first aperture gate electrode having the aperture formed therethrough, and in another embodiment, the gate electrode structure includes first and second aperture gate electrodes having respective first and second reticulations therein so as to frame the aperture.