Abstract: The present disclosure discloses a semiconductor structure having an insulating layer disposed on a wafer active surface of a semiconductor wafer for covering the wafer active surface. The insulating layer may be a protective layer in some embodiments and a cover layer in other embodiments. The insulating layer has via openings to expose contact pads for leading out electrical connections. In particular, the via openings are formed by a multi-step etching process (such as a two-step etching process) without damaging the contact pads. The two-step etching process includes a first laser etching process using normal pulse (P) and normal energy to form partial via openings in the cover layer. The second etching process includes either a laser etching process using low P and low E or a plasma etching process. The second etching process avoids damaging the contact pads.

Abstract: A complementary metal oxide semiconductor (CMOS) device embedded with micro-electro-mechanical system (MEMS) components in a MEMS region. The MEMS components, for example, are infrared (IR) thermoconforms. The device is encapsulated with a CMOS compatible IR transparent cap to hermetically seal the MEMS sensors in the MEMS region. The CMOS cap includes a base cap with release openings and a seal cap which seals the release openings.

Abstract: A wafer-level buffer layer is disclosed. The wafer-level buffer layer is configured to prevent cracking and chipping the back-end-of-line (BEOL) dielectric during wafer singulation process. The wafer-level buffer layer is a composite wafer-level buffer layer with a vibration damping agent. The vibration damping agent includes a polymer-based base layer with fillers. The damping agent absorbs or dampens the vibration of the saw blade during dicing to prevent cracking and chipping of the BEOL dielectric.

Abstract: Efficient 3D geospatial mapping is disclosed. A 3D geospatial map of an area of interest is generated from 2D satellite imagery. The 2D imagery is preprocessed to generate a point cloud of the area of interest. The point cloud is optimized by removing atmospheric clouds and shadows. A 3D geographical information system (GIS) map with multiple levels of details (LOD) is generated.

Abstract: The present disclosure discloses a method of packaging a chip and a chip package structure. The method of packaging the chip includes: forming a protective layer on a front surface of a chip to be packaged; mounting the chip to be packaged formed with the protective layer on the front surface on a first carrier, the back surface of the chip to be packaged facing upwards and a front surface thereof facing towards the first carrier; forming a first encapsulation layer, the first encapsulation layer being formed on the back surface of the chip to be packaged and the exposed first carrier; and detaching the first carrier to exposed the protective layer.

Abstract: Device and method of forming the device are disclosed. The method includes providing a substrate prepared with a complementary metal oxide semiconductor (CMOS) region and a sensor region. A substrate cavity is formed in the substrate in the sensor region, the substrate cavity including cavity sidewalls and cavity bottom surface and a membrane which serves as a substrate cavity top surface. The cavity bottom surface includes a reflector. The method also includes forming CMOS devices in the CMOS region, forming a micro-electrical mechanical system (MEMS) component on the membrane, and forming a back-end-of-line (BEOL) dielectric disposed on the substrate having a plurality of interlayer dielectric (ILD) layers. The BEOL dielectric includes an opening to expose the MEMS component. The opening forms a BEOL cavity above the MEMS component.

Abstract: A complementary metal oxide semiconductor (CMOS) device integrated with micro-electro-mechanical system (MEMS) components in a MEMS region is disclosed. The MEMS components, for example, are infrared (IR) thermosensors. The MEMS sensors are integrated on the CMOS device heterogeneously. For example, a CMOS wafer with CMOS devices and interconnections as well as partially processed MEMS modules is bonded with a MEMS wafer with MEMS structures, post CMOS compatibility issues are alleviated. Post integration process to complete the devices includes forming contacts for interconnecting the sensors to the CMOS components as well as encapsulating the devices with a cap wafer using wafer-level vacuum packaging.

Abstract: This document describes systems and methods for treating and recovering water from feed solutions using a multilayer module with an expansion chamber. The multilayer module comprises a feed spacer layer, a permeate spacer layer and a membrane layer, wherein water vapor evaporated from the feed solution in the feed spacer passes through the membrane layer into the permeate spacer layer. The expansion chamber receives the water vapor from the permeate spacer layer and the feed solution from the feed spacer layer.

Abstract: An isolation system and isolation device are disclosed. An illustrative isolation device is disclosed to include a transmitter circuit, a detector circuit, a first wire bond, and a second wire bond. The detector circuit is configured to generate a first current in accordance with a first signal. The first wire bond is configured to receive the first current from the transmitter circuit to generate a magnetic flux. The second wire bond is configured to receive the magnetic flux. An induced current in the second wire bond is then detected in the detector circuit. The detector circuit is configured to generate a reproduced first signal, as an output of the detector circuit.

Abstract: The present disclosure provides a chip packaging method and a package structure. The chip packaging method comprises: forming a wafer conductive layer on a wafer active surface of a wafer; forming a protective layer having certain material properties on the wafer conductive layer, the protective layer encapsulating the wafer conductive layer and exposing a front surface of the wafer conductive layer; separating (such as cutting) the wafer formed with the wafer conductive layer and the protective layer to form a die; attaching (such as adhering) the die onto a carrier; forming a molding layer having certain material properties on a die back surface of the die on the carrier; removing (such as stripping off) the carrier; forming a panel-level conductive layer electrically connected with the wafer conductive layer; and forming a dielectric layer.

Abstract: The present disclosure provides a graphical watermark, a method and an apparatus for generating a graphical watermark, and a method and an apparatus for authenticating a graphical watermark. The graphical watermark includes: a plurality of graphical markers carrying position and pose information, and identity information of the graphical watermark; and a watermark pattern provided between a pair of graphical markers.

Abstract: The embodiments of the present disclosure relate to a packaging method, a panel assembly, a wafer package and a chip package. The semiconductor device packaging method includes: providing at least one wafer including a first surface and a second surface opposite to each other and a side surface connecting the first surface and the second surface, the first surface being an active surface; forming a connection portion on the side surface of the at least one wafer around the wafer, the wafer and the connection portion forming a panel assembly, the connection portion includes a third surface on the same side of the first surface of the wafer and a fourth surface on the same side as the second surface of the wafer, the third surface and the first surface forming a to-be-processed surface of the panel assembly; and forming a first dielectric layer on the first surface of the wafer. The packaging method of the embodiments of the present disclosure may improve packaging efficiency and utilization of a wafer.

Abstract: The present invention relates to hyper-branched compounds, a method of synthesizing the hyper-branched compounds and applications of the hyper-branched compounds. The hyper-branched compounds of the present invention include hyper-branched fluorinated compounds, hyper-branched fluorinated graphene and hyper-branched amine functionalized graphene oxide.

Abstract: A depth detection apparatus includes: an emitting assembly for emitting a speckle light signal to a detection object, where the emitting assembly is configured to cause the speckle light signal to generate positive distortion; an imaging lens for imaging, to a photoelectric sensor, a depth light signal returned after the speckle light signal strikes the detection object, wherein the imaging lens is configured to cause the imaging of the depth light signal to generate negative distortion; and a photoelectric sensor for converting the depth light signal into an electrical signal, wherein a difference between an absolute value of a distortion amount of the negative distortion and an absolute value of a distortion amount of the positive distortion does not exceed 0.05, and the negative distortion and the positive distortion each are distortion having a distortion amount whose absolute value is greater than or equal to 0.03.

Abstract: The present disclosure provides a two-dimensional barcode generating method, a two-dimensional barcode verification method, a two-dimensional barcode verification server, and a two-dimensional barcode, and relates to the field of two-dimensional barcode. For the two-dimensional barcode provided by the present disclosure, a generic module in an existing two-dimensional barcode has been replaced by an encryption module, wherein the encryption module includes an encryption area and a first identification area. The encryption area contains an encryption identifier recorded therein for verifying the authenticity of the two-dimensional barcode, and the first identification area contains a first recognition identifier recorded therein for presenting information carried by the two-dimensional barcode.

Abstract: This document describes systems and methods for treating and recovering water from feed solutions using a membrane module that has a plurality of hollow fiber membranes encapsulated in a collection chamber and an expansion chamber that is connected to the outlet of the membrane module.

Abstract: A stator of an SRM is disclosed. The stator includes two or more pairs of diametrically opposite stator poles and two or more stator windings Each stator winding is wound around each pair of diametrically opposite stator poles. The winding can be energized to generate magnetic flux within one stator pole of the pair of diametrically opposite stator poles along a radial axis thereof. The magnetic flux emanates out of a face of the stator pole. The stator further includes a permanent magnet disposed in the stator pole for diverting the magnetic flux to emanate at least substantially from a side surface of the stator pole. A motor and a vehicle including the stator are also disclosed. A method of manufacturing the stator is further disclosed.

Abstract: The present disclosure provides a chip packaging method and a package structure. The chip packaging method comprises: forming a protective layer having material properties on a die active surface of a die; attaching (such as adhering) the die in which the die active surface is formed with the protective layer onto a carrier, the die active surface facing the carrier, and a die back surface of the die facing away from the carrier; forming an encapsulation layer having material properties to encapsulate the die; removing (such as stripping off) the carrier to expose the protective layer; and forming a conductive layer and a dielectric layer.

Abstract: A sealed capsule for blending and dispensing an initially solid food product holds a blending component with embedded food product. Actuating the blending component through an electronic control system causes the food product to be blended within the capsule. One or more feedback control mechanisms are used to guarantee a desired consistency of the blended food product. Provided are structural features of the capsule, and methods of using its contents to blend and dispense soft-serve products.

Abstract: The embodiments of the present disclosure relate to a packaging method, a panel assembly, a wafer package and a chip package. The semiconductor device packaging method includes: providing at least one wafer including a first surface and a second surface opposite to each other and a side surface connecting the first surface and the second surface, the first surface being an active surface; forming a connection portion on the side surface of the at least one wafer around the wafer, the wafer and the connection portion forming a panel assembly, the connection portion includes a third surface on the same side of the first surface of the wafer and a fourth surface on the same side as the second surface of the wafer, the third surface and the first surface forming a to-be-processed surface of the panel assembly. The packaging method of the embodiments of the present disclosure may improve packaging efficiency and utilization of a wafer.