Abstract: Disclosed are a magnetic coupling-based inter-chip wireless communication interface structure and method for three-dimensional stacked chips. The interface structure includes a master chip and at least one slave chip, wherein the master chip and all the slave chips are vertically stacked; the slave chip includes a clock receiving module, a data transmitting module, and a data receiving module; the master chip includes a clock transmitting module, a data transmitting module, and a data receiving module. The solution herein makes use of the magnetic coupling relationship between on-chip spiral inductors of different chips in a vertical direction to simultaneously transmit data and clock signals. The communication method herein modulates each bit of digital signal into a differential bi-directional non-return-to-zero pulse train and performs decision and data parsing at the receiving end by a high-speed dynamic comparator.

Abstract: Disclosed is an inductive coupling system and method for adaptive control of power transfer for a wireless three-dimensional stacked chip package. The system includes a slave chip and a master chip connected via inductive coupling; the system for adaptive control of power transfer herein shifts a load feedback voltage received by the slave chip into a feedback voltage data codeword through a level decision circuit, and the system can load the feedback voltage data codeword onto a data link of the system and feedback same to the master chip. In the present disclosure, the master chip includes a DPID control circuit controls a voltage-controlled oscillator and a frequency divider to adjust the frequency of an input clock in an energy transfer system so as to achieve adaptive control of the transmitting power of a transmitting chip.

Abstract: The present invention discloses a microminiature image acquisition and processing system package structure and a preparation method thereof. This structure includes optical coated glass, a CMOS chip, a wafer Re-Distribution Layer and a molding layer, the first surface of the CMOS chip is provided with a photosensitive and microlens region and a metal bonding pad, and a through-silicon via is etched in a second surface of the CMOS chip until it extends to the metal bonding pad on the first surface; the wafer Re-Distribution Layer covers the second surface of the CMOS chip and extends to the through-silicon via. The structure and the method of the present invention are integrated with wafer-level package and SIP integrated package technologies to achieve single package of the whole device, thereby greatly reducing the system complexity and power consumption, reducing the overall product size and signal path, and improving the image anti-interference capability.

Abstract: The present invention provides a dual-substrate antenna package structure and a method for manufacturing the same. The package structure includes a main substrate and at least one antenna substrate. The antenna substrate is provided on a pad of the main substrate by an array of solder balls placed on the antenna substrate, at least one chip is electrically connected to the main substrate, and metal wiring provided on the main substrate electrically connects the pad to the chip. The array of solder balls includes support solder balls and conventional solder balls, and the support solder balls have a melting point high than 250° C. A spacing distance between the antenna substrate and the main substrate can be kept stable during the reflow soldering process and subsequent processes because the support solder balls having the high melting point can always maintain the stability of the structure during the reflow soldering process.

Abstract: The present application discloses a double-sided SiP packaging structure and a manufacturing method thereof, wherein the double-sided SiP packaging structure comprises a substrate, a first packaging structure arranged on the substrate, and a second packaging structure arranged below the substrate; the second packaging structure comprises a chip, interposer and a molding material; a conductive structure array is arranged on an upper surface of the interposer; the interposer is arranged below the substrate through the conductive structure array; a space region among a lower surface of the substrate, the chip and the interposer is filled with the molding material; a conductive bonding pad array is arranged on the lower surface of the interposer; and a groove is formed in a part of region between the conductive bonding pad and an edge contour of the interposer.

Abstract: The present invention provides a package structure with an inductor and a manufacturing method thereof, the inductor and the interconnection component are used as n second package module, and stacked with other components such as the first package module to form a stack-like package structure. The first package module is provided with other electronic elements. Then the first and second package modules can be synchronously subjected to package manufacturing, which improves the production efficiency. Additionally, the soldering balls with different heights are formed on the first faces of the interconnecting structural component and the inductive device by adjusting the consumption of soldering paste, which make the second faces of the inductor and the interconnection component are coplanar, then inductor with different heights can form a flat interconnecting plane, which makes the sequential process such as pasting and mounting can be conveniently performed.

Abstract: The present invention provides a package structure and a method for manufacturing the same. The package structure includes at least two electrical elements, a second reconstruction layer, and a metal lead frame, wherein at least one of the electrical elements is a chip, at least one of the electrical elements has a first reconstruction layer, and the second reconstruction layer has a smaller pin pitch than that of the metal lead frame; the second reconstruction layer has a first surface and a second surface, a functional surface of the electrical element is disposed on and connected to the first surface, and at least one of the electrical elements is connected to the second reconstruction layer; and the second surface is disposed on and connected to the metal lead frame. A fan-out package structure is formed on the metal lead frame, which improves the heat dissipation capacity of the chip.