Abstract: A memory driving device includes a first switch, a voltage detecting circuit, and a switch array. The first switch includes a first output terminal and a first control terminal, and the first output terminal provides an output voltage for a memory unit. The voltage detecting circuit is coupled to the first output terminal, and configured to detect the output voltage, and generates a control signal according to the output voltage, wherein the control signal changes in real time according to the changing of the output voltage. The switch array includes a plurality of second switches, and the second switches are coupled to the first control terminal. At least one of the second switches is turned on according to the control signal so as to adjust a voltage of the first control terminal for regulating a waveform of the output voltage.

Abstract: A method of fabricating layered structure is disclosed. A basal layer is formed. A laminate is formed on the basal layer, and the laminate includes a device layer, a sacrificial layer and a protection layer stacked in sequence. The device layer, the sacrificial layer and the protection layer are etched to obtain a patterned laminate. A first dielectric layer covering a lateral surface of the patterned laminate is formed. Part of the first dielectric layer and part of the protection layer are removed by polishing. The protection layer of the patterned laminate is etched to expose the sacrificial layer. A through hole in the first dielectric layer is formed to expose the basal layer. The sacrificial layer of the patterned laminate is etched to form an opening in the first dielectric layer, and the opening exposes a top surface of the device layer.

Abstract: A method of fabricating layered structure is disclosed. A basal layer is formed. A laminate is formed on the basal layer, and the laminate includes a device layer, a sacrificial layer and a protection layer stacked in sequence. The device layer, the sacrificial layer and the protection layer are etched to obtain a patterned laminate. A first dielectric layer covering a lateral surface of the patterned laminate is formed. Part of the first dielectric layer and part of the protection layer are removed by polishing. The protection layer of the patterned laminate is etched to expose the sacrificial layer. A through hole in the first dielectric layer is formed to expose the basal layer. The sacrificial layer of the patterned laminate is etched to form an opening in the first dielectric layer, and the opening exposes a top surface of the device layer.

Abstract: A method of fabricating layered structure is disclosed. A basal layer is formed. A laminate is formed on the basal layer, and the laminate includes a device layer, a sacrificial layer and a protection layer stacked in sequence. The device layer, the sacrificial layer and the protection layer are etched to obtain a patterned laminate. A first dielectric layer covering a lateral surface of the patterned laminate is formed. Part of the first dielectric layer and part of the protection layer are removed by polishing. The protection layer of the patterned laminate is etched to expose the sacrificial layer. A through hole in the first dielectric layer is formed to expose the basal layer. The sacrificial layer of the patterned laminate is etched to form an opening in the first dielectric layer, and the opening exposes a top surface of the device layer.

Abstract: A phase change memory and a method of fabricating the same are provided. The phase change memory includes a lower electrode, an annular heater, an annular phase change layer, and an upper electrode. The annular heater is disposed over the lower electrode. The annular phase change layer is disposed over the annular heater, and the annular phase change layer and the annular heater are misaligned in a normal direction of the lower electrode. The upper electrode is disposed over the annular phase change layer. The present disclosure simplifies the manufacturing process of the phase change memory, reduces the manufacturing cost, and improves the manufacturing yield. In addition, a contact surface between the heater and the phase change layer of the phase change memory of the present disclosure is very small, so that the phase change memory has an extremely low reset current.

Abstract: A memory device includes a memory array, write drivers and a controller. The memory array includes a plurality of memory units respectively arranged in a plurality of bit lines. The write drivers generate a plurality of write bit signals respectively inputted to the bit lines. The controller provides a voltage mode control signal and a current mode control signal. The controller is electrically coupled to the write drivers. Each of the write drivers generates a respective write bit signal of each of the write drivers according to the voltage mode control signal and the current mode control signal. When each of the memory units is in a set state, the controller outputs the voltage mode control signal and the current mode control signal to the write drivers. When each of the memory units is in a reset state, the controller outputs the voltage mode control signal to the write drivers.

Abstract: A memory device includes a memory array, a bit line driving circuit, a word line driving circuit, a read/write circuit, a controller, and a reference driving circuit. The memory array includes several memory units. The bit line driving circuit is configured to interpret a memory bit address and to drive a bit line. The word line driving circuit is configured to interpret a memory word address and to drive a word line. The read/write circuit is configured to read, set, or reset the memory units. The controller is configured to switch the memory array to work in a single memory unit mode or a dual memory unit mode. The reference driving circuit is configured to drive a reference line, wherein the reference line comprises several reference units, and the reference line and the reference units are located in the memory array.

Abstract: A sensing-amplifier device includes a first input terminal, a second input terminal, a reference unit, and a sense amplifier. The reference unit is configured to provide a reference signal. The switching unit is selectively coupled to the first input terminal, the second input terminal, and a reference unit. The sense amplifier includes two terminals. The two terminals of the sense amplifier are coupled to the first input terminal and the second input terminal respectively by switching of the switching unit so as to operate in a twin memory unit mode, or one terminal of the sense amplifier is coupled to the first input terminal or the second input terminal and the other terminal of the sense amplifier is coupled to the reference unit by switching of the switching unit so as to operate in a single memory unit mode.

Abstract: A memory driving device includes a first switch, a voltage detecting circuit, and a switch array. The first switch includes a first output terminal and a first control terminal, and the first output terminal provides an output voltage for a memory unit. The voltage detecting circuit is coupled to the first output terminal, and configured to detect the output voltage, and generates a control signal according to the output voltage, wherein the control signal changes in real time according to the changing of the output voltage. The switch array includes a plurality of second switches, and the second switches are coupled to the first control terminal. At least one of the second switches is turned on according to the control signal so as to adjust a voltage of the first control terminal for regulating a waveform of the output voltage.

Abstract: A memory device includes first and second memory arrays, first and second bit line driving circuits, first and second word line driving circuits, a read/write circuit, a controller, and first and second reference driving circuits. The first and second memory arrays include several memory units. The first and second bit line driving circuits are configured to interpret a memory bit address and drive a bit line. The first and second word line driver circuits are configured to interpret the memory word address and drive the word line. The read/write circuit is configured to read, set or reset the memory units. The controller is configured to switch the first and second memory arrays to work in a single memory unit mode or a dual memory unit mode. The first and second reference driving circuits are configured to drive reference rows.

Abstract: A memory driving circuit is disclosed herein. The memory driving circuit includes a programmable current source, a reference voltage generation unit and a voltage comparator unit, The programmable current source generates a second current according to a first current. The second current flows into a memory cell, and produces a device voltage at the input of the memory cell. The reference voltage generation unit generates a crystal voltage. The voltage comparator unit compares the device voltage with the crystal voltage and sends out a control signal to control the programmable current source. The first current and the second current are adjusted by the control signal so that the shape of the current pulse of SET operation to the memory cell is well controlled.