Abstract: A system and method introduce a variable thermal resistance to test and burn in apparatus. The system and method provide an efficient design for more accurate temperature control of integrated circuits. A system for testing integrated circuit (IC) packages comprises a plurality of IC testing socket bases arranged on a testing board and configured to receive a plurality of IC packages. A plurality of IC testing socket lids are arranged to attach to the testing board. Each IC testing socket lid comprises a temperature sensor to thermally contact the IC package and measure a surface temperature of the IC package, a heat sink is placed into either proximity to or directly in contact with the IC package, and an electronic controller to receive signals from the temperature sensor.

Abstract: A method and apparatus for conducting burn-in testing of semiconductors is provided. A semiconductor device under test (DUT) with a plurality of contact pads is placed into a seal carrier. The seal carrier is then placed within a plurality of first inner walls of an outer housing of a burn-in testing apparatus that is fastened to a cold plate through a printed circuit board (PCB). The seal carrier has a plurality of second inner walls that define a recessed cavity. A lid is placed over the seal carrier and fastened to the outer housing to seal the recessed cavity. The recessed cavity is pneumatically pressurized to force the contact pads of the semiconductor DUT into electrical contact with a plurality of resiliently compressible pins of a socket of the PCB. The socket is then energized to conduct a burn-in test of the semiconductor DUT.

Abstract: A system and method introduce a variable thermal resistance to test and burn in apparatus. The system and method provide an efficient design for more accurate temperature control of integrated circuits. A system for testing integrated circuit (IC) packages comprises a plurality of IC testing socket bases arranged on a testing board and configured to receive a plurality of IC packages. A plurality of IC testing socket lids are arranged to attach to the testing board. Each IC testing socket lid comprises a temperature sensor to thermally contact the IC package and measure a surface temperature of the IC package, a heat sink is placed into either proximity to or directly in contact with the IC package, and an electronic controller to receive signals from the temperature sensor.

Abstract: Apparatus and methods provide burn-in testing for semiconductors. A burn-in test apparatus (1) may include an outer housing forming an aperture with a test socket to receive a tile or wafer. The tile or wafer may include semiconductor device(s) for burn-in testing. The apparatus may include a thermal control unit to regulate testing temperature and/or drive electronics for powering the socket. The apparatus may include an inlet for gas pressure from a pressure source. The apparatus may include a lid covering the aperture when a tile/wafer is at the test socket. The apparatus may include a seal carrier in the aperture to form a pressure chamber with a surface of the tile. The pressure chamber may pneumatically couple with the inlet. Pressure of the pressure chamber may act upon the tile/wafer to urge a device under testing into thermal and/or electrical contact with the socket for conducting the burn-in test.

Abstract: Apparatus and methods provide burn-in testing for semiconductors. A burn-in test apparatus (1) may include an outer housing forming an aperture with a test socket to receive a tile or wafer. The tile or wafer may include semiconductor device(s) for burn-in testing. The apparatus may include a thermal control unit to regulate testing temperature and/or drive electronics for powering the socket. The apparatus may include an inlet for gas pressure from a pressure source. The apparatus may include a lid covering the aperture when a tile/wafer is at the test socket. The apparatus may include a seal carrier in the aperture to form a pressure chamber with a surface of the tile. The pressure chamber may pneumatically couple with the inlet. Pressure of the pressure chamber may act upon the tile/wafer to urge a device under testing into thermal and/or electrical contact with the socket for conducting the burn-in test.

Abstract: Apparatus and methods provide burn-in testing for semiconductors. A burn-in test apparatus (1) may include an outer housing forming an aperture with a test socket to receive a tile or wafer. The tile or wafer may include semiconductor device(s) for burn-in testing. The apparatus may include a thermal control unit to regulate testing temperature and/or drive electronics for powering the socket. The apparatus may include an inlet for gas pressure from a pressure source. The apparatus may include a lid covering the aperture when a tile/wafer is at the test socket. The apparatus may include a seal carrier in the aperture to form a pressure chamber with a surface of the tile. The pressure chamber may pneumatically couple with the inlet. Pressure of the pressure chamber may act upon the tile/wafer to urge a device under testing into thermal and/or electrical contact with the socket for conducting the burn-in test.

Abstract: A method for testing integrated circuit devices and loading such devices into a test board for further testing and an apparatus therefor is disclosed. The method allows for selection between two modes of operation. In a first mode, the integrated circuit devices are subjected to an electrical test before being placed into the test board for further testing. In a second mode, the integrated circuit devices are tested after being placed in the test board. The apparatus allows for the selection between the first mode and the second mode. In either mode, information about the tested devices and the sockets in the test board is used to load the test boards intelligently. Intelligent loading means that devices under test (DUTs) are not placed in bad sockets and devices that do test bad are removed from the test board, with an option of replacing the failed DUT with another DUT before subsequent environmental testing of the DUTs in the test board is carried out.

Abstract: A method for testing integrated circuit devices and loading such devices into a test board for further testing and an apparatus therefor is disclosed. The method allows for selection between two modes of operation. In a first mode, the integrated circuit devices are subjected to an electrical test before being placed into the test board for further testing. In a second mode, the integrated circuit devices are tested after being placed in the test board. The apparatus allows for the selection between the first mode and the second mode. In either mode, information about the tested devices and the sockets in the test board is used to load the test boards intelligently. Intelligent loading means that devices under test (DUTs) are not placed in bad sockets and devices that do test bad are removed from the test board, with an option of replacing the failed DUT with another DUT before subsequent environmental testing of the DUTs in the test board is carried out.

Abstract: A method for testing integrated circuit devices and loading such devices into a test board for further testing and an apparatus therefor is disclosed. The method allows for selection between two modes of operation. In a first mode, the integrated circuit devices are subjected to an electrical test before being placed into the test board for further testing. In a second mode, the integrated circuit devices are tested after being placed in the test board. The apparatus allows for the selection between the first mode and the second mode. In either mode, information about the tested devices and the sockets in the test board is used to load the test boards intelligently. Intelligent loading means that devices under test (DUTs) are not placed in bad sockets and devices that do test bad are removed from the test board, with an option of replacing the failed DUT with another DUT before subsequent environmental testing of the DUTs in the test board is carried out.

Abstract: A method for testing integrated circuit devices and loading such devices into a test board for further testing and an apparatus therefor is disclosed. The method allows for selection between two modes of operation. In a first mode, the integrated circuit devices are subjected to an electrical test before being placed into the test board for further testing. In a second mode, the integrated circuit devices are tested after being placed in the test board. The apparatus allows for the selection between the first mode and the second mode. In either mode, information about the tested devices and the sockets in the test board is used to load the test boards intelligently. Intelligent loading means that devices under test (DUTs) are not placed in bad sockets and devices that do test bad are removed from the test board, with an option of replacing the failed DUT with another DUT before subsequent environmental testing of the DUTs in the test board is carried out.