Abstract: An extender card is plugged into a memory module socket on a personal computer (PC) motherboard. The extender card has a test socket that receives a memory module under test. The extender card has an intercepting EEPROM chip that receives device-select lines from the motherboard. One of the device-select lines from the motherboard to a module EEPROM chip on the memory module is blocked by the extender card and altered so that the intercepting EEPROM chip is read by the motherboard rather than the module EEPROM chip. A memory configuration is read from the intercepting EEPROM chip. The memory module is tested by the motherboard using the configuration from the intercepting EEPROM chip on the extender card. The module EEPROM chip is then programmed with the configuration by altering the intercepted device-select address to select the module EEPROM chip and not the intercepting EEPROM chip.

Abstract: A production test machine pre-screens panels of memory modules for shorts and leakage and other D.C. parameters. Memory modules are constructed as part of a panel of 6 or so modules formed on the same substrate. The modules are connected together by links of the substrate. The D.C. tests are performed on memory modules before separation from the panel (de-panelization), while the modules are still connected together by the panel links. Using parallel testing, a whole panel of modules can be D.C. tested at the same time. Failing modules can then be marked or noted, and the good modules separated from the panel links and sent to a more expensive A.C. tester for functional testing. The spacing or pitch of test heads on the D.C. tester can be adjusted for different sizes of panels.

Abstract: A test system has many motherboards. Each motherboard has a reverse-mounted test adaptor board that contains a test socket. A robotic arm inserts a memory module into the test socket, allowing the motherboard to execute programs to test the memory module. A test chamber surrounds the test socket. Compressed air is regulated and routed to local heaters near each motherboard. The local heaters pass the air over a resistive heating element to heat the air. The heated air is then directed into the test chamber to heat the memory module being tested. A local valve controls the air flow through the local heater. A host computer receives temperature measurements from each test chamber and adjusts the local heater and valve to maintain a desired test temperature. The motherboards can be cooled by cooling fans while the memory modules being tested are heated.

Abstract: Repeater units in a stack are identical. Each repeater unit has an internal repeater and an internal bridge. The repeater stack is dual-speed, with each repeater connecting to a 10 Mbps (10M) backplane bus and to a 100 Mbps (100M) backplane bus in the stack's chassis. The internal repeater has a 10M repeater circuit that connects 10M ports to the 10M bus, and a 100M repeater circuit that connects 100M ports to the 100M bus. Ports are configured for either 10M or 100M operation. Data from 10M ports is repeated to all other 10M ports and to the 10M bus, but not to 100M ports or the 100M bus. Instead, a 10M port is connected to the internal bridge, which is also connected to a 100M port. The internal bridge stores and forwards packets to and from the 10M port and the 100M port. Only one internal bridge in the stack is configured to link the 10M and 100M ports. Other internal bridges are configured to connect a cascading port to the internal repeater. The cascading port is buffered by the internal bridge.

Abstract: A test system has many motherboards. Each motherboard has a reverse-mounted test adaptor board that contains a test socket. A robotic arm inserts a memory module into the test socket, allowing the motherboard to execute programs to test the memory module. A test chamber surrounds the test socket. Compressed air is regulated and routed to local heaters near each motherboard. The local heaters pass the air over a resistive heating element to heat the air. The heated air is then directed into the test chamber to heat the memory module being tested. A local valve controls the air flow through the local heater. A host computer receives temperature measurements from each test chamber and adjusts the local heater and valve to maintain a desired test temperature. The motherboards can be cooled by cooling fans while the memory modules being tested are heated.

Abstract: Memory modules such as SIMMs and DIMMs are automatically tested by a target-system motherboard such as a PC motherboard. An automated SIMM/DIMM handler is connected to a handler adaptor board that is mounted to the back or solder-side of the PC motherboard. The relatively flat surface of the solder-side of the PC motherboard allows close mounting of the handler. One or more of the SIMM sockets on the motherboard is removed to provide mounting holes for the handler adaptor board. The handler adaptor board provides electrical connection from the module-under-test (MUT) in the handler to the removed SIMM socket on the PC motherboard. The handler adaptor board provides a slight spacing or offset from the solder-side surface of the PC motherboard's substrate, allowing the handler to be plugged directly into tester-connectors on the handler adaptor board.

Abstract: Memory modules are tested using a test assembly with a personal computer (PC) motherboard. The motherboard is mounted upside-down with its solder-side up to a metal plate using standoffs. A memory-module socket on the motherboard is removed. An opening is made in the metal plate above the removed socket. A well is attached to the metal plate at the opening. The well supports a test adaptor board below the metal plate so that the test adaptor board has a closer spacing to the motherboard than does the metal plate. The test adaptor board has a test socket that receives a module being tested. Pins from the test adaptor board are plugged into the holes of the removed socket on the motherboard, but mounted on the reverse, solder side of the motherboard rather than the component side. The cables, components, and expansion boards of the motherboards are hidden below the metal plate and motherboard, and can be cooled without cooling the memory module in the test socket.

Abstract: Margin testing of memory modules uses a personal computer (PC) motherboard. A test adaptor board has a test socket that receives a memory module under test. Pins from the test adaptor board are plugged into holes of a removed memory-module socket on the motherboard, mounted on the reverse, solder side of the motherboard. The test adapter board has a voltage regulator that controls the power-supply (Vcc) voltage applied to the module under test. A delay circuit on the test adapter board varies the phase delay of a clock to the memory module under test. Margin control signals are generated by a controller card in the PC's expansion slots, to control Vcc and clock delay to the module under test without changing the motherboard's Vcc voltage. The test program executing on the PC motherboard writes to the controller card to adjust voltage and delay, allowing Vcc and setup and hold margins to be tested.

Abstract: Each stacked repeater has two activity ports that are daisy chained to the activity ports of other repeaters in the stack. Each activity port has an input and an output. The two activity ports connect to the next repeater above and the next repeater below in the stack. Each repeater examines its local network ports to computer stations such as PC's to determine if any are inputting data to the repeater. When any local port is inputting data, the repeater activates both of its activity-port outputs. When no local port is inputting data, the repeater simply passes each activity-port's input through to the other activity-port's output. Thus the activity-port output indicates when either the repeater or an earlier repeater in the chain has a local port inputting data.

Abstract: Data is compressed in an industry-standard local-area network (LAN) such as IEEE 802.2 or 802.3. Compression occurs at a low level, in the data link layer just above the physical layer. The data in the packet is compressed, but the source and destination addresses are not compressed. A type/length field which indicates the length of the data field is adjusted for the new compressed length, while a frame checksum which was calculated for the uncompressed data is re-generated for the compressed data. Thus the packet with the compressed data has the length and checksum adjusted for the newly compressed data so that the packet appears normal to other layers of the LAN protocol. A status byte may be added to the compressed data to disable compression on a remote LAN station. The compressed data packet is compatible with hubs to other LANs and bridges to WANs.