Patents Assigned to Komatsu Electronics Metals Co., Ltd.
  • Patent number: 6019837
    Abstract: A temperature sensor 42 is provided in a furnace 11, measuring temperature above a molten liquid 24 put in a crucible 12 to check proceedings of evaporation of oxygen vaporized from a free surface 44 of the molten liquid 24. From the data, and considering the relation with the oxygen dissolved into the crucible 12, the oxygen concentration in the molten liquid 24 can be found and the amount of oxygen taken into a single silicon crystal 40 pulled up from the molten liquid 24 can be figured out.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: February 1, 2000
    Assignees: Komatsu Electronic Metals Co., Ltd., Mitsubishi Materials Silicon Corporation, Kagaku Gijutsu Sinkou Jigyo Dan, Toshiba Ceramics Co., Ltd.
    Inventors: Susumu Maeda, Keisei Abe, Kazutaka Terashima, Hideo Nakanishi
  • Patent number: 6007625
    Abstract: This invention provides a method and a apparatus capable of manufacturing single crystals with an oxygen density of less than 12.times.10.sup.17 atoms/cm.sup.3 or less than 10.times.10.sup.17 atoms/cm.sup.3, and wherein the oxygen density of the single crystal produced is uniformly distributed along its longitudinal axis. The electrical power inputted into the main heater 6 surrounding the quartz crucible 4 and the top heater 9 shaped like a reverse frustrated cone and disposed above the quartz crucible 4, is controlled to keep the temperature of the melt 5 in a preset range during the process of pulling up the single crystal silicon 10. When combining the main heater 6 and the top heater 9, the heat emitted from the main heater 6 can be kept small, and the heat load on the quartz crucible 4 and the amount of oxygen released from the quartz crucible 4 and dissloved into melt 5 can be reduced.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: December 28, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Junsuke Tomioka, Hiroshi Inagaki, Fumitaka Ishikawa
  • Patent number: 6006737
    Abstract: A plurality of wires are stretched in parallel through wire supplying-winding apparatuses and wire-tension adjusting apparatuses. A semiconductor-crystal bar is affixed on an ascent/descent table via a feeding table. The ascent/descent table is capable of being driven to ascend or descend by the ascent/descent apparatus. The wires and the semiconductor-crystal bar are dipped into a high-insulation oil, and discharging is created therebetween to perform cutting. If the resistance of the semiconductor-crystal bar exceeds 1 .OMEGA..multidot.cm, used inert gas is filled into a space within the interior space of an airtight vessel. Then, the high-insulation oil is heated by heaters and is kept at a temperature higher than 150.degree. C. to reduce the resistance of the semiconductor-crystal bar. Therefore, cutting is easily performed. The used inert gas can prevent fire from occurring due to the flaming of the high-insulation oil.
    Type: Grant
    Filed: January 29, 1998
    Date of Patent: December 28, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Yoshikazu Hayashi, Masanori Hashimoto
  • Patent number: 6004860
    Abstract: An SOI substrate and a method for fabricating the same are provided to sharpen the departing angle at the circumference of the active substrate, and provide the active substrate with a uniform thickness. An attached wafer of the present invention is formed by processing the upper side of the base substrate so that its thickness increases from the center to the circumference, and attaching the active substrate to the processed side of the base substrate. The unattached portion of the attached wafer is removed. Then mirror processing is performed to provide the active substrate with a substantially uniform thickness along the processed side of the base substrate.
    Type: Grant
    Filed: August 30, 1996
    Date of Patent: December 21, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Tadashi Ogawa, Akihiro Ishii, Yuichi Nakayoshi
  • Patent number: 6004393
    Abstract: A temperature sensor 42 is provided in a furnace 11, measuring temperature above a molten liquid 24 put in a crucible 12 to check proceedings of evaporation of oxygen vaporized from a free surface 44 of the molten liquid 24. From the data, and considering the relation with the oxygen dissolved into the crucible 12, the oxygen concentration in the molten liquid 24 can be found and the amount of oxygen taken into a single silicon crystal 40 pulled up from the molten liquid 24 can be figured out.
    Type: Grant
    Filed: January 22, 1999
    Date of Patent: December 21, 1999
    Assignees: Komatsu Electronic Metals Co., Ltd., Mitsubishi Materials Silicon Corporation, Kagaku Gijutsu Sinkou Jigyo Dan, Toshiba Ceramics Co., Ltd.
    Inventors: Susumu Maeda, Keisei Abe, Kazutaka Terashima, Hideo Nakanishi
  • Patent number: 6002262
    Abstract: A halogen lamp of illuminance 150,000 lux or greater and wavelength 1129 nm or less is provided in the vicinity of a probe of an electrostatic capacitative flatness measuring instrument, and illuminates the surface of the wafer under measurement. When the light enters into the bulk, it is converted to excitation energy, which converts the valence electrons of the silicon into conduction electrons. Since the free electrons or positive holes generated from the silicon are overwhelmingly more than the dopant or oxygen donors, the wafer exhibits characteristics similar to metal. That is, electrons are uniformly distributed in all parts of the wafer. When, in this state, the upper face and lower face of the wafer are measured, the relative dielectric constant is fixed in all locations, so all the changes in electrical amount can be measured as changes in distance between the wafer and the probe.
    Type: Grant
    Filed: July 19, 1996
    Date of Patent: December 14, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Junichiro Higashi, Robert K. Graupner
  • Patent number: 6001007
    Abstract: A backing pad 7 is secured on the bottom of a ceramic plate 6. A template 1 is secured on the bottom of the backing pad 7. The thickness of the template 1 successively diminishes from the inner periphery wall 12 of the central accommodation opening for restraining the semiconductor wafer, toward the outer periphery wall 13 of the template 1, so that the bottom of the template 1 is inclined and the cross section of the template 1 is tapered.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: December 14, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Masahiko Maeda, Yuichi Nakayoshi
  • Patent number: 5997641
    Abstract: The hold member has a small-diameter portion and a large-diameter portion. An inner cylinder and an outer cylinder are disposed around the hold member in a concentric manner. The upper end of the hold member is affixed to a wire and suspended therefrom. A clearance is formed between the small-diameter portion and the inner cylinder. Clearances are created between the outer peripheral surface of the inner cylinder and the inner peripheral surface of the outer cylinder.
    Type: Grant
    Filed: December 8, 1997
    Date of Patent: December 7, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Mitsunori Kawabata, Yoshinobu Hiraishi, Mitsuo Usukubo, Ayumi Suda
  • Patent number: 5997635
    Abstract: An apparatus and a method for fabricating a single-crystal semiconductor by means of CZ method are provided for improving the quality control through the modification of thermal cycle of a pulled single-crystal semiconductor. The apparatus includes a ring after heater which is capable of elevation. The method decreases a temperature gradient to smaller than 20.degree. C./cm, and preferably under 15.degree. C./cm, when the pulled single-crystal semiconductor is cooled from 1200.degree. C. to 1000.degree. C. The after heater therefore heats the single-crystal semiconductor where there is a temperature of 100-300.degree. C. lower than the range of 1200-1000.degree. C. A thermal shelter is provided to retain a temperature gradient of larger than 20.degree. C./cm when the single-crystal semiconductor is within the temperature range between the melting point and 1250.degree. C. The after heater and the shelter can be raised to an upper portion when polysilicon blocks are charged and a twisting step is carried out.
    Type: Grant
    Filed: January 22, 1998
    Date of Patent: December 7, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Toshimichi Kubota, Toshiro Kotooka, Makoto Kamogawa
  • Patent number: 5995217
    Abstract: A laser is irradiated on the surface of a semiconductor wafer while a stage mounted on the semiconductor wafer is moved, and scattering lights emitted from the surface of the semiconductor wafer is received by the receiving device, and an intensity distribution of the scattering lights is measured. The intensity distribution is processed by the controller so as to obtain a defect density of the semiconductor wafer.
    Type: Grant
    Filed: September 3, 1998
    Date of Patent: November 30, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventor: Noriko Watanabe
  • Patent number: 5990022
    Abstract: The evaluating method includes: dipping a mirror-polished silicon wafer in a dilute hydrofluoric acid; washing the surface of the silicon wafer; subjecting the surface-washed silicon wafer to a heat treatment in an oxygen atmosphere to form a thermal oxidation film; forming a predetermined number of polycrystalline silicon electrodes having a predetermined area on the thermal oxidation film; applying a voltage to each electrode between the predetermined number of polycrystalline silicon electrodes and the silicon wafer; and judging the quality of the mirror-polishing process of the silicon wafers in accordance with the breakdown electric field intensity of the leakage current obtained by measuring the oxide film insulation.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: November 23, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Hisami Motoura, Eiichi Asano
  • Patent number: 5972726
    Abstract: An oxide film is formed of a silicon substrate, and then the oxide film is cleaned together with the silicon substrate. Afterwards, a medical fluid is dropped on the oxide film which has been cleaned, and then the oxide film is dissolved by the medical fluid to collect contaminants included in the oxide film.
    Type: Grant
    Filed: June 17, 1998
    Date of Patent: October 26, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Yukio Saitoh, Shigenori Toshiyoshi, Tokitsugu Zushi, Takanori Nishimura
  • Patent number: 5971191
    Abstract: A container for packing semiconductor wafer is provided which has superior airtightness to prevent contamination of the wafers by air. A gasket groove is formed on the case of the container. A gasket is inserted within the gasket groove. The gasket contains protrusions that assist in providing an airtight seal. The case and a lid are securely fastened together by the engagement of four clips within respective clip recesses that are formed in the container and lid.
    Type: Grant
    Filed: February 14, 1997
    Date of Patent: October 26, 1999
    Assignees: Komatsu Electronic Metals Co., Ltd., Komatsu Plastics Industrial Co., Ltd.
    Inventors: Naoki Yamada, Mitsuo Terada, Kiyoshi Nishizawa, Jun Uchida
  • Patent number: 5968260
    Abstract: A method for fabricating a single-crystal semiconductor by means of CZ method is disclosed. The method separates the single-crystal semiconductor from the melt by increasing the lift rate when the growth of a crystal body is finished. By controlling the lift rate, the single-crystal semiconductor is then gradually cooled within a range of an arbitrary crystal temperature, thereby forming a concave separated surface. The single-crystal semiconductor is cooled at a rate of lower than 35.degree. C./min when the temperature of the separated surface is within a range between the melting point and 1000.degree. C., or by keeping the temperature of the separated surface within a range between 1250.degree. C. and 1000.degree. C. for more than 30 minutes. Therefore, no dislocation is introduced in the crystal body, and productivity is improved.
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: October 19, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Toshiaki Saishouji, Tetsuhiro Iida, Kouzou Nakamura, Toshimichi Kubota, Junsuke Tomioka
  • Patent number: 5968262
    Abstract: When the pulling speed is V(mm/min), the temperature gradient along the crystal axis within the temperature range from the melting point of silicon to 1300.degree. C. is G1 (.degree. C./mm), the temperature gradient along the crystal axis within the temperature range from 1150.degree. to 1080.degree. C. is G2 (.degree. C./mm), and the octahedral-shaped void density is d (pieces/cm.sup.3), crystals are grown under a condition satisfying:V/G1>0.581.times.V.times.G2-(d-4.3.times.10.sup.3)/2.65.times.10.sup.6 and V/G1>0.25.In this way, the defect density is reduced to less than 1.times.106 pieces/cm.sup.3 and silicon single crystals having superior gate oxide integrity and semiconductor device yield are obtained.
    Type: Grant
    Filed: November 21, 1997
    Date of Patent: October 19, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Toshiaki Saishouji, Kouzou Nakamura, Toshimichi Kubota, Junsuke Tomioka
  • Patent number: 5963821
    Abstract: This invention provides a method for efficiently making semiconductor wafers having uniform thickness where the thickness of the back side does not influence the front side and where the front side of the wafer is capable of being distinguished from the back side. A semiconductor ingot is sliced to obtain wafers. The sliced surfaces of the wafers are flattened. The flattened wafer is etched in alkaline etching solution. Both the front and back sides of the etched wafer are polished using a double sided polishing apparatus so that the front side is a mirror surface and an unevenness remains on the back side to distinguish the front and back sides, thereof. The polished wafer is cleaned.
    Type: Grant
    Filed: October 29, 1997
    Date of Patent: October 5, 1999
    Assignee: Komatsu Electronic Metal Co., Ltd.
    Inventors: Fumitaka Kai, Masahiko Maeda, Kenji Kawate
  • Patent number: 5953620
    Abstract: A method for fabricating a bonded SOI wafer is provided in which no void is produced during a waiting period from the completion of a bonding step to the start of a bonding thermal processing step without a special restriction. The method for fabricating a bonded SOI wafer includes a bonding step in which an active wafer, which has been single- or both-side mirror polished and thermal oxidation processed to form an insulating layer of a predetermined thickness, is pressed and bonded to a single- or both-side mirror polished base wafer; and a bonding thermal processing step for carrying out a bonding thermal processing for bonding the wafer, in which a hydrophobic processing step for the base wafer and a hydrophilic processing step for the active wafer are carried out before the bonding step.
    Type: Grant
    Filed: December 13, 1996
    Date of Patent: September 14, 1999
    Assignee: Komatsu Electronics Metals Co., Ltd.
    Inventors: Hirotaka Katou, Hiroshi Furukawa, Kazuaki Fujimoto
  • Patent number: 5951759
    Abstract: This invention provides a apparatus and a method of pulling up single crystals, which respond to the weight increase of semiconductor single crystal produced by the CZ method. The retaining wire wind-up mechanisms 11, 12; multiple pairs of guide pipes 4a, 4c capable of being moved upward or downward with respect to the seed holder 1; and a plurality of retaining wires 13, 15, each retaining wire passing through one pair of the guide pipes and having its central portion to be bent into a "U" shape are provided in the central portion of the lifting wire 5. The single crystal 17 can be retained by the retaining wire 13, 15, if the guide pipes 4a, 4c are driven to move downward and the "U" shaped portions of the retaining wires 13, 15 are driven to engage with the necked portion 17b so as to lift single crystal 17. The load is determined based on the detected value coming from the weight sensors installed on the means for winding up the retaining wires.
    Type: Grant
    Filed: October 15, 1997
    Date of Patent: September 14, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Hiroshi Inagaki, Fumitaka Ishikawa
  • Patent number: 5948159
    Abstract: When the silicon single crystal is pulled up, the nucleation rate of the void cluster is obtained from the forming energy of the cluster of the vacancies in the silicon single crystal. The growth shrinkage of the cluster is obtained basing on the deviation of the flowing-into amount to the cluster of the vacancies and the self-interstitials, and the pulling-up speed or the temperature distribution of the furnace is modified to inhibit the growth of the cluster so as to inhibit the grown-in defects of the silicon single crystal.
    Type: Grant
    Filed: March 19, 1998
    Date of Patent: September 7, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Kozo Nakamura, Toshiaki Saishoji, Toshimichi Kubota
  • Patent number: 5942033
    Abstract: A crystal-clamping fixture 30 is suspended by a pulling up mechanism 1 through the use of wires. The crystal-clamping fixture 30 includes a box 31 and a plurality of holding rods 32. The box 31 has two openings formed on its top and bottom sides. The reduced portion 2a, the enlarged portion 2b and the necked portion 2c formed beneath the seed crystal 5 are allowed to penetrate through the two openings during the pulling up operation. A plurality of "S" shaped slots 31a, 31b are formed on the lateral sides of the box 31. The holding rods 32 capable of rotating along the path of the "S" shaped slots 31a, 31b are horizontally disposed within the box 31 by inserting their two end portions through the "S" shaped slots 31a, 31b. The holding rods kept restrained at the upper ends of the "S" shaped slots are pushed out by the conic surface formed at the upper part of the enlarged portion 2b and rotate and descend to reach the lower ends of the "S" shaped slots.
    Type: Grant
    Filed: March 26, 1998
    Date of Patent: August 24, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Shoei Kurosaka, Hiroshi Inagaki, Shigeki Kawashima, Junsuke Tomioka