Abstract: The reliability and operability of semiconductor devices is improved using a current source that advantageously exhibits stability during startup, operates at low voltages and can be used with a variety of integrated circuit devices including operational amplifiers. An example embodiment of the present invention is directed to a PTAT current sourcing circuit that includes first and second current paths and a folded current-drawing arrangement in which first and second bipolar transistors provide a substantially-reduced minimum operating voltage. In a more particular example embodiment, the PTAT current sourcing circuit comprises a first current path including a pair of cascoded MOS-type transistors inter-coupled at a first node, and including another MOS-type circuit in series with the pair of cascoded MOS-type transistors.

Abstract: Useful to inhibit reverse engineering, semiconductor devices and methods therefore include formation of two active regions over a substrate region in the semiconductor device. According to an example embodiment, a dopable link, or region, between two heavily doped regions can be doped to achieve a first polarity type, with the two heavily doped regions of the opposite polarity. If dictated by design requirements, the dopable region is adapted to conductively link the two heavily doped regions. A dielectric is formed over the dopable region and extends over a portion of each of the two heavily doped regions to inhibit silicide formation over edges of the dopable region. In connection with a salicide process, a silicide is then formed adjacent the dielectric and formed over another portion of the two heavily doped regions.

Abstract: A method and apparatus for reducing power consumption of a receiver of a communications device that does not change the global hardware of the device and uses the current master clock to lower the clock frequency. In an example embodiment, a method directed to reducing power consumption of a receiver of a communications device during an idle state. The receiver has an internal power source and a corresponding base unit. The method includes generating a clock signal that has an output frequency that varies, the frequency being higher in an active state and lower in an inactive state, such that the receiver consumes more power during the active state then when in the inactive state. Power consumption by the receiver is reduced by dynamically and synchronously switching the clock frequency to a lower clock frequency. Receiver power consumption is a function of the power consumed during the active and inactive states and the duration of the idle state.

Abstract: An arrangement controls an IC designed with multiple “core” circuits, such as multiple CPUs, with each core circuit including its own TAP controller. According to one example embodiment, multiple test-access port (TAP) controllers coupled to a common interface are controlled by adapting each TAP controller to receive input signals, determine if the TAP controller is enabled, and generate status signals and test signals. An output circuit responds to the TAP controllers by outputting one of the test signals respectively provided by the multiple TAP controllers, and a link module is used to maintain one of the TAP controllers enabled at a given time. The above-embodiment is useful, for example, in connection with IC applications that require an increasing number of core circuits without increasing the circuit area of the IC and/or the number of IC pins, and can be implemented to avoid changing existing structures of TAP controllers.

Abstract: A semiconductor device is manufactured using an ashing process to eliminate the adverse effects of contamination, such as amine-airborne contamination. Consistent with one embodiment of the present invention, the semiconductor device is formed by applying a DUV-type photoresist over the wafer surface, exposing the photoresist to DUV light, baking the wafer, and then ashing the wafer in a highly-oxidized environment to remove insoluble amine-related resist.

Abstract: A hybrid one time pad encryption and decryption apparatus with methods for encrypting and decrypting data wherein a one time random number pad provides high security encryption. The random number sequence is encrypted using DES, RSA or other technique and embedded in the message as a function of the random pad itself. This generates an encryption message that is impervious to attempts to directly decode the message text as the message is randomly dispersed throughout a message and the message contains as much quasi-random data as text. The message is also relatively impervious to attempts to decode the cipher, as the cipher is randomly interrupted by the encrypted data.

Abstract: An appatatus for enhancing transport packet demultiplexing and distribution in a digital transport demultiplexing system that inputs a stream of digital multimedia transport packets is provided. The demultiplexing apparatus performs the demultiplexing operation by transferring data packets into and out of circular data queues. These circular queues comprise a contiguous block of memory which are defined by a queue starting address, a queue size, a read pointer, and a write pointer. When data packets are written to and read from a circular queue, the sequential addressing of the queue will automatically rollover from the highest memory location within the queue to the lowest memory location when the sequential addresses move through the circular queue. The addressing of the various queues and sharing of a transport stream bus is handled by a memory arbiter and queue manager.

Abstract: A rapid silicon processing arrangement significantly decreases the time from initial design to market introduction. Consistent with one embodiment of the present invention, rapid silicon processing arrangement uses a deconfigurable and extendible reference-chip development platform that includes a programmable device such as an electronically reconfigurable gate array and an off-platform bus for communicating with external devices. The reference-chip development platform can be deconfigured by deselecting communicative activity by one or more of functional block macros. The external devices can be used with the reference-chip development platform to test a hardware representation of the synthesized of the functional block macros in the programmable device within the reference-chip development platform as extended by the off-platform bus. The approach significantly decreases the development time, from initial design to market introduction.

Abstract: A method for simultaneously generating one time pads and an apparatus which implements the method to produce a secure encryption system. The method and apparatus use the Diffie-Hellman key exchange algorithm to produce a one time pad rather than exchange keys. This makes it practical to generate one time pads for use in secure transmissions.

Abstract: An arrangement controls an IC designed with multiple “core” circuits, such as multiple CPUs, with each core circuit including its own TAP controller and with multiple TAP controllers enabled at a time. For applications typically requiring that control be transferred between such TAP controllers, one embodiment of the present invention configures a TLM-based design such that multiple TAP controllers can be simultaneously enabled. This alleviates the need to actually transfer the control from one TAP controller to the next. To maintain consistency with the IEEE JTAG recommendation, the TLM-based design is configured such that only one TAP is enabled upon reset. After reset, the TLM controls the multiply-enabled TAP controllers. Another specific example implementation is directed to a circuit control arrangement for such a multi-core IC having each TAP controller generate status and test signals in response to input signals directed to each of the multiple TAP controllers.

Abstract: The present invention is directed to a method and apparatus for cleaning and enhancing CMP polishing pads. According to an example embodiment of the present invention, a fluid source supplies cleaning elements to a CMP pad conditioner arrangement at pressure of about 20 PSI. A dispensing arrangement is coupled to the fluid source and is adapted to disperse the cleaning elements and to dispense the elements onto a CMP pad. The high-pressure cleaning of the CMP pad improves the ability to clean the pad over existing methods, reduces processing defects, increases the pad life, and improves the uniformity of the polish rate.

Abstract: In an example embodiment, a method for manufacturing a semiconductor device having shallow trench isolation comprises forming a trench region in a substrate having a substantially planar bottom, a first and second sidewall. In the trench region, the method forms a dielectric liner on the bottom and the first and second sidewalls. The dielectric liner is a silicon nitride compound. The dielectric liner minimizes the anomalous increases in threshold voltage with width (Vt versus W) owing to transient enhanced up-diffusion of the channel profile induced by source/drain implant damage. In addition, the anomalous increase in Vt versus W associated with the formation of an interstitial gradient in sub-micron devices is reduced. By using a nitrided liner, Vt roll off due to boron segregation is also minimized.

Abstract: According to an example embodiment, the present invention is directed to a method for manufacturing a semiconductor device. The device includes a conductive underlayer. A sub-micron via or contact path and a dummy via or dummy contact path are dry etched. The endpoint of the dry etching process is optically detected, and the etching process is stopped responsive to the detection of the endpoint. By etching a dummy via or contact in addition to the submicron via or contact, this example embodiment facilitates endpoint detection for dry etching sub-micron features in semiconductor devices, which is otherwise difficult or even impossible in the submicron regime.