Abstract: A bit synchronizer for NRZ data wherein a loop gain of a phase locked loop in the bit synchronizer is not varied sensitively to bit pattern and rate of the NRZ data and a voltage control led oscillator in the bit synchronizer oscillates synchronously with a multiple of a frequency of an external reference clock pulse even in the absence of NRZ data transitions or over a wide range of variation of a clock frequency of the voltage controlled oscillator, so that the NRZ data and clock can be recovered stably, According to the invention, the bit synchronizer comprises a phase comparator, a first gain controller, a frequency comparator, a second gain controller, a N-frequency divider, a low pass filter and a voltage controlled oscillator.
Type:
Grant
Filed:
March 16, 1993
Date of Patent:
July 4, 1995
Assignees:
Electronics and Telecommunications Research Institute, Krea Telecommunication Authority
Inventors:
Bhum C. Lee, Kwon C. Park, Hang G. Bahk