Abstract: A wafer stage overlay error map is created using standard overlay targets and a special numerical algorithm. A reticle including a 2-dimensional array of standard overlay targets is exposed several times onto a photoresist coated silicon wafer using a photolithographic exposure tool. After exposure, the overlay targets are measured for placement error using a conventional overlay metrology tool. The resulting overlay error data is then supplied to a software program that generates a 2-dimensional wafer stage distortion and yaw overlay error map.
Type:
Grant
Filed:
June 26, 2001
Date of Patent:
May 11, 2004
Assignee:
Lael Instruments
Inventors:
Adlai Smith, Bruce McArthur, Robert Hunter, Jr.