Abstract: A method for manufacturing a heat conductive adhesive film includes: forming a non-solid heat conductive adhesive layer with cured particles on a substrate; forming several bumps on the non-solid heat conductive adhesive layer while performing curing, so as to yield the heat conductive adhesive film with several bumps. A heat conductive adhesive film and an OLED panel are provided. Several bumps are formed on a flat surface of the heat conductive adhesive film, thus increasing the surface area of the heat conductive adhesive film such that heat from the heat generating unit can be duly discharged.

Abstract: An improved touch screen provides enhanced electrical performance and optical quality. The electrodes on the touch screen are made of a mesh of conductors to reduce the overall electrode resistance thereby increasing the electrical performance without sacrificing optical quality. The mesh electrodes comprise a mesh pattern of conductive material with each conductor comprising the mesh having a very small width such that the conductors are essentially invisible to the user of the touch screen.

Abstract: An improved touch screen has enhanced optical performance and aesthetic quality. The electrodes on the touch screen employ additional fine traces of conductive material to reduce the overall electrode trace resistance to increase electrical performance without sacrificing optical quality. The additional fine traces of conductive material may be placed on the top of the ITO traces or in channels inside the boundaries of the ITO traces. The additional traces preferably run the length of the ITO traces to reduce the resistance in the longer dimension. Further, the additional traces are very small in width such that in the aggregate they cover only a small portion of the ITO electrode trace in lateral dimension to reduce the visibility of the additional traces. The conductive material may also be formed as a plurality of geometric shapes substantially forming a line in the longer dimension of the transparent conductive traces to reduce the visibility of the conductive material.

Abstract: An improved touch screen has enhanced optical performance and aesthetic quality. The sense electrodes and other traces on the touch screen are made less invisible to the user by substantially filling the space between the conductive traces or electrodes with isolated regions that match the light transmission characteristics of the electrodes. In capacitive and resistive touch screens, the space between ITO electrodes and other traces on the substrate is substantially filled with ITO to match the electrodes. The space between electrodes is preferably filled with isolated regions of ITO formed in a pattern. The isolated regions in the pattern may be shaped and the electrodes notched to create non-linear spaces to further reduce the visibility of the pattern. Further, the space between ITO traces can be filled with irregular-shaped ITO regions to further reduce the visibility of the space.

Abstract: A capacitive touch screen has fewer manufacturing steps to reduce the cost of manufacture. The touch screen has ITO conductor traces that are resistance matched to maintain the accuracy of the touch screen while reducing the cost of manufacture. In addition, offset pattern printing is used to apply an optically matched insulative coating over the conductive traces to eliminate the need for other process steps to connect the conductive traces for the capacitive sense lines.

Abstract: An LCD is constructed such that a side edge of a common electrode disposed on an entire surface of an upper substrate and a pad disposed on the lower substrate facing the upper substrate are not overlapped. The LCD includes an active panel having a gate pad and a source pad spaced at a predetermined distance D from the edge of the color filter panel which faces the active panel.

Abstract: The present invention is related to a method of crystallizing an amorphous silicon layer and a crystallizing apparatus thereof which crystallize an amorphous silicon layer using plasma. The present invention includes the steps of depositing an inducing substance for silicon crystallization on an amorphous silicon layer by plasma exposure, and carrying out annealing on the amorphous silicon layer to the amorphous silicon layer. The present invention includes a chamber having an inner space, a substrate support in the chamber wherein the substrate support supports a substrate, a plasma generating means in the chamber wherein the plasma generating means produces plasma inside the chamber, and a heater at the substrate support wherein the heater supplies the substrate with heat.

Abstract: A thin-film transistor includes a substrate, and a gate including a double-layered structure having first and second metal layers provided on the substrate, the first metal layer being wider than the second metal layer by 1 to 4 &mgr;m. A method of making such a thin-film transistor includes the steps of: depositing a first metal layer on a substrate, depositing a second metal layers directly on the first metal layer; forming a photoresist having a designated width on the second metal layer; patterning the second metal layer via isotropic etching using the photoresist as a mask; patterning the first metal layer by means of an anisotropic etching using the photoresist as a mask, the first metal layer being etched to have the designated width, thus forming a gate having a laminated structure of the first and second metal layers; and removing the photoresist.

Abstract: A thin-film transistor includes a substrate, and a gate including a double-layered structure having first and second metal layers provided on the substrate, the first metal layer being wider than the second metal layer by 1 to 4 &mgr;m. A method of making such a thin-film transistor includes the steps of: depositing a first metal layer on a substrate, depositing a second metal layers directly on the first metal layer; forming a photoresist having a designated width on the second metal layer; patterning the second metal layer via isotropic etching using the photoresist as a mask; patterning the first metal layer by means of an anisotropic etching using the photoresist as a mask, the first metal layer being etched to have the designated width, thus forming a gate having a laminated structure of the first and second metal layers; and removing the photoresist.

Abstract: A thin-film transistor includes a substrate, and a gate including a double-layered structure having first and second metal layers provided on the substrate, the first metal layer being wider than the second metal layer by 1 to 4 &mgr;m. A method of making such a thin-film transistor includes the steps of: depositing a first metal layer on a substrate, depositing a second metal layers directly on the first metal layer; forming a photoresist having a designated width on the second metal layer; patterning the second metal layer via isotropic etching using the photoresist as a mask; patterning the first metal layer by means of an anisotropic etching using the photoresist as a mask, the first metal layer being etched to have the designated width, thus forming a gate having a laminated structure of the first and second metal layers; and removing the photoresist.

Abstract: A method of manufacturing a liquid crystal panel prevents the introduction of static electricity from the exterior of a liquid crystal panel. According to the method, edges of a lower glass substrate on which a liquid crystal material layer and an upper glass substrate are disposed are dipped into an etchant. At this time, the ends of the test electrodes formed on the lower glass substrate are removed. The ends of the test electrodes are removed, and consequently an introduction path of stripe-shaped defect is not generated within the liquid crystal panel. Also, the yield of the liquid crystal panel is greatly improved.

Abstract: A multi-domain vertical alignment liquid crystal display device includes upper and lower substrates having upper and lower alignment layers, a pixel electrode on the lower substrate, and a liquid crystal layer between the upper and lower alignment layers. The upper alignment layer is alignment-treated to define a specified alignment direction. The pixel electrode is arranged to define a desired pattern of slits or floating electrodes. The liquid crystal layer includes liquid crystal molecules having negative dielectric anisotropy (&Dgr;∈).

Abstract: A thin-film transistor includes a substrate, and a gate including a double-layered structure having first and second metal layers provided on the substrate, the first metal layer being wider than the second metal layer by 1 to 4 &mgr;m. A method of making such a thin-film transistor includes the steps of: depositing a first metal layer on a substrate, depositing a second metal layers directly on the first metal layer; forming a photoresist having a designated width on the second metal layer; patterning the second metal layer via isotropic etching using the photoresist as a mask; patterning the first metal layer by means of an anisotropic etching using the photoresist as a mask, the first metal layer being etched to have the designated width, thus forming a gate having a laminated structure of the first and second metal layers; and removing the photoresist.

Abstract: A thin film transistor includes a substrate, a gate electrode on the substrate, a gate insulating layer on the substrate and covering the gate electrode, an active layer on the gate insulating layer, an ohmic contact layer on the active layer and not overlapping the gate electrode, and a source electrode and a drain electrode connected to the ohmic contact layer. Each of the source electrode and the drain electrode has a double-layered structure of a first metal layer having tensile stress and a second metal layer having compressive stress.

Abstract: A method of forming an insulating layer pattern in a liquid crystal display which enables the formation of an insulating layer pattern on a substrate under a low temperature without the need of expensive equipment and complicated processes, wherein the formation speed of the insulating layer is accelerated. The method includes the steps of forming an organic thin layer containing silicon on an insulated substrate, exposing the thin layer to a gaseous ambience including, oxygen, generating a plurality of oxygen radicals and silicon radicals by applying ultraviolet rays to the thin layer using a mask having a predetermined pattern, forming an insulating layer by reacting the silicon radicals with the oxygen radicals, and defining an insulating layer pattern by removing a portion of the thin layer free of the ultraviolet rays.

Abstract: A liquid crystal display includes a first substrate having a plurality of pixel electrodes arranged in a matrix, a plurality of row terminals and common electrode terminals arranged on one side of two adjacent sides of the first substrate, a plurality of column terminals and common electrode terminals arranged on the other side of the two adjacent sides of the first substrate; a second substrate arranged to be opposite to the first substrate and to interpose a liquid crystal display with the first substrate and having a counter electrode for performing liquid crystal display by applying a voltage across the pixel electrodes and the counter electrode. The conductive region being connected to at least one of the common electrode terminals to apply a common potential to the counter electrode.

Abstract: A method of manufacturing a substrate of an LCD prevents defective patterning of pixel electrodes and improves an aperture ratio of pixels by simplifying the steps of manufacturing a substrate of an LCD. A protection layer is formed on a substrate and the protection layer includes a light developable organic(BCB) layer which is patterned directly by exposing using a mask instead of patterning with a photo resist. The portion of the light developable organic layer remaining on the bottom part of contact holes after patterning is etched using a gate insulating layer. The etching process using the gate insulating layer is performed partially in order to expose the surface of the gate pad by using a plasma gas having about 85% CF4 and about 15% O2.

Abstract: A method of mounting a liquid crystal display module thereof which secures an upper sash including the liquid crystal display module to a lower sash in a notebook personal computer. An arm coupled to one end of a fixed rod by a hinge is arranged to be positioned between a side wall of the upper sash and a side wall of the lower sash. A screw goes through from the side wall of the upper sash, via the arm, to the side wall of the liquid crystal display module.

Abstract: A liquid crystal display includes a first substrate having a plurality of pixel electrodes arranged in a matrix, a plurality of row terminals and common electrode terminals arranged on one side of two adjacent sides of the first substrate, a plurality of column terminals and common electrode terminals arranged on the other side of the two adjacent sides of the first substrate; a second substrate arranged to be opposite to the first substrate and to interpose a liquid crystal display with the first substrate and having a counter electrode for performing liquid crystal display by applying a voltage across the pixel electrodes and the counter electrode. The conductive region being connected to at least one of the common electrode terminals to apply a common potential to the counter electrode.

Abstract: A liquid crystal display includes a first substrate having a plurality of pixel electrodes arranged in a matrix, a plurality of row terminals and common electrode terminals arranged on one side of two adjacent sides of the first substrate, a plurality of column terminals and common electrode terminals arranged on the other side of the two adjacent sides of the first substrate; a second substrate arranged to be opposite to the first substrate and to interpose a liquid crystal display with the first substrate and having a counter electrode for performing liquid crystal display by applying a voltage across the pixel electrodes and the counter electrode. The conductive region being connected to at least one of the common electrode terminals to apply a common potential to the counter electrode.