Abstract: Phase slippage of a test clock signal and the direction of such slippage are digitally detected, accumulated, and displayed and/or recorded. A test clock signal is recovered from one digital carrier signal. A reference clock signal is recovered from another digital carrier signal. From the test clock signal, first and second binary signals are generated at a frequency phase synchronized to the test clock signal. The second signal is shifted in phase from the first signal. Responsive to the reference clock signal, the states of the first and second signals are repeatedly sampled such that the sampled states are representative of the phase relationship between the test clock signal and the reference clock signal. Successive samples of the states of the first and second signals are compared to detect unit interval phase shifts between the test clock signal and the reference clock signal. The phase shifts detected by the comparison are accumulated at successive samples are compared to represent phase slippage.