Abstract: A distributed memory switch system for transmitting packets from source ports to destination ports, comprising: a plurality of ports including a source port and a destination port wherein a packet is transmitted from the source port to the destination port; a memory pool; and an interconnection stage coupled between the plurality of ports and the memory pool such that the interconnection stage permits a packet to be transmitted from the source port to the destination port via the memory pool.

Abstract: A multistage analog circuit for independently controlling a bias current in each stage of the multistage analog circuit having an input stage, an intermediate stage, and an output stage, includes a first current source which controls the input stage of the circuit, a second current source which controls the intermediate stage of the circuit, and a third current source which controls the output stage of the circuit. The bias current in each stage of the circuit is set by the first, second, and third current sources. An output voltage of the circuit is capable of remaining the same when the first current source is changed to affect an input transconductance of the circuit.

Abstract: A converter or a resampler used in a digital communication system converts a first digital signal representing an analog signal into a second digital signal representing the same analog signal. The converter includes a converter filter and a timing circuit. The timing circuit provides a first clock generated from a second clock, and a phase control signal for controlling the conversion of the converter filter. The timing circuit is preferably a numerical controlled oscillator (NCO) and includes an accumulator for generating the first clock from the second clock and a phase offset, and a phase calculator which receives the phase offset to generate a phase control signal. The phase control signal includes a plurality of phase weighting signals, a plurality of control signals, and an interpolation signal. The first digital signal is selectively convoluted with the phase weighting signals, which is controlled by the control signals.

Abstract: A network repeater having automatic speed switching capability. The repeater includes a first repeater logic for connecting devices operating at the first rate to a first backplane, a second repeater logic for connecting devices operating at the second rate to a second backplane, and a port switching fabric, coupled to the first and second repeater logic, for determining the transmission rate of a signal at a port and routing the signal to one of the repeater logic according to the transmission rate determination. The repeater includes a serial controller for accessing internal management counters, LEDs for providing status information about the repeater and a media access controller for controlling functions including the transmission loopback and reception of Ethernet frames.

Abstract: A pulse width distortion correction logic level converter converts differential logic while preserving the pulse width of the original signal. The converter converts a differential input signal to a single-ended signal having a same pulse width as the differential input signal. The present invention receives and converts the differential input signal at a first converter and a second converter, wherein the first converter generates a first output signal, and the second converter generates a second output signal, respectively. Latching the first output signal of the first converter and the second output signal of the second converter produces a fill swing single-ended output signal having the same pulse width as the input differential signal. The first output signal sets the latching device with an edge of the first output signal of the first converter and resets the latching device with an edge of the second output signal of the second converter.

Abstract: A multistage analog circuit for independently controlling a bias current in each stage of the multistage analog circuit having an input stage, an intermediate stage, and an output stage, includes a first current source which controls the input stage of the circuit, a second current source which controls the intermediate stage of the circuit, and a third current source which controls the output stage of the circuit. The bias current in each stage of the circuit is set by the first, second, and third current sources. An output voltage of the circuit is capable of remaining the same when the first current source is changed to affect an input transconductance of the circuit.

Abstract: A network device automatically detects the best protocol a network will support. The network device includes a driver for transmitting data, a receiver for receiving data, and a port operationally coupled to the driver and receiver. The network device further includes negotiation logic coupled to the driver and receiver for selecting a protocol in coordination with other network devices. The network device further includes error detection logic and backs down to a lower transmission rate if errors are detected after the initial negotiation of the selected protocol.

Abstract: A communication system includes a timing circuit which generates phase conversion information from a transmitter to transfer data from a first clock domain to a second clock domain, and a receive phase calculation circuit which utilizes the phase information from the transmitter to transfer data from the second clock domain to the first clock domain. The timing circuit includes a transmit (TX) numerical controlled oscillator (NCO) and a modulo indicator, and the receive phase calculation circuit calculates a receive phase based on a modulo signal.

Abstract: A jitter suppression apparatus in a data transmission system includes a phase detector circuit to determine a plurality of phase errors between sync pulses of a data line and sync pulses of a reference line, and an adapted phase error offset circuit, coupled to the phase detector circuit, to generate a plurality of phase error offsets and adaptively offset the plurality of phase error offsets. The jitter suppression apparatus may also include a stuff/delete slicer, coupled to the adapted phase error offset circuit, to generate a plurality of stuff/delete signals such that a framer can determine what type of data frames to send to a communication channel of the data transmission system. A jitter suppression method includes steps of detecting a phase error, computing a phase error offset, and filtering out the phase error offset. An integrator may be used to filter out the phase error offset input to the stuff/delete slicer.

Abstract: A method and apparatus for providing a self-sustaining precise voltage and current feedback biasing loop. The present invention provides a circuit for initially biasing the bandgap and master bias current generator at startup. The feedback biasing loop has loop dynamics that are chosen such that the gain of the positive feedback loop is less than one so that the loop will not oscillate under normal operation after power-up.

Abstract: A direct conversion type transceiver system incorporates an offset correction and automatic gain control system. The automatic gain control system includes an amplifier amplifying a baseband signal which is directly converted from a received incoming RF signal, a feedback offset canceller controllably canceling DC offset, an automatic gain controller controlling gain of the amplifier, and a feed forward offset canceller coupled to a signal peak detector. The signal peak detector controlling the automatic gain controller and the feed forward offset canceller simultaneously, the feed forward offset canceller further canceling the DC offset.

Abstract: A system and method for regulating the duty cycle of a digital clock signal derived from an oscillator signal. The oscillator signal is DC-biased to a DC value representing an average DC value of an ideal digital clock signal having a 50% duty cycle. The DC-biased oscillator signal is compared to a reference voltage. The digital clock signal is generated as a substantially square wave signal having first and second logic levels, and is generated in response to the comparison of the DC-biased oscillator signal and the reference voltage. The DC component of the generated digital clock signal is then used as the reference voltage.

Abstract: An offset window detector that senses the sum of two signals and compares the result to a reference voltage for attenuating an offset voltage and producing a desired gain. The primary design issues of the detector is to achieve a very low voltage offset and a low power dissipation. The detector is part of the offset circuits in the I/Q path of a wireless receiver. The maximum input signal and the minimum input signal are the positive and negative peak values of the in-phase or the quadrature signal paths. They are generated by a peak detector. The offset signal can be estimated by the addition of the maximum input signal with the minimum input signal. This resulting offset signal is compared to the reference voltage to determine if the resulting signal is greater than a maximum reference voltage, less than a minimum reference voltage or within the maximum and minimum voltages. A reference voltage generator creates the desired voltages within a desired tolerance.

Abstract: A combined, parallel adaptive equalizer/echo canceller is disclosed. The equalizer/canceller receives at least one input signal which is split into n taps. The n taps are multiplied by corresponding n tap coefficients to produce n tap output signals. The n tap output signals are then processed through an additive pipeline to produce a filter output signal. The additive pipeline provides low latency by processing the nth most recent tap output signal n clock cycles from the filter output signal. The combined FIR filter structure is made fully adaptive using delayed LMS coefficient adaptation. Tap coefficients are updated using an error signal and delayed versions of the input signal. The error signal is a product of a calculated error and a negative adaptation factor. The delay is equal to a sum of n+1 cycles.

Abstract: A common mode bias voltage generator apparatus and method includes a plurality of MOSFET-based transistors and a plurality of resistors configured and arranged to provide a half of a supply voltage with a predetermined low output impedance while using relatively little power and circuit area.

Abstract: An activation method for adaptive equalization in a data transceiver including a plurality of adaptive filters wherein the adaptive filters are adapted with a first type of adaptation method to obtain initial convergence of the adaptive filters during an initial activation of the data transceiver and a second type of adaptation method to optimize performance of recovering the received signals in the presence of noise.

Abstract: A VCO system for equalizing a positive frequency deviation and a negative frequency deviation by using two varactors is described. The VCO system includes an active circuit and an oscillating circuit. The active circuit includes a first input, a second input coupled to ground and an output. The oscillating circuit is coupled to the output of the active circuit, including: a first varactor controlled by a first variable voltage; a second varactor controlled by a second variable voltage, connected in parallel to the first varactor; and an inductor connected in parallel to the first varactor and to the second varactor. An output signal of the oscillating circuit is fed back to the first input of the active circuit. The output signal of the oscillating circuit has a variable frequency in response to first and second variable voltages of the first and second varactors, respectively.

Abstract: A conversion circuit in a transceiver system is capable of converting a single-ended input voltage signal to balanced differential output signals. An input voltage signal can be referenced to the ground (zero voltage) GND and can travel both above and below the zero voltage. A plurality of feedback circuits, having a plurality of transistors and a plurality of resistances, disposed and coupled in a mirror image, to boost an input impedance to an output impedance of a gain of one of the transistors, to isolate an output load from an input of the conversion circuit, and to provide a voltage gain from the input to an output determined by the plurality of resistances.

Abstract: The invention relates in general to error correcting programmable pulse generator, and more particularly to a programmable pulse generator that removes errors due to manufacturing tolerances, power supply variation, and temperature. A method of modifying a signal from a source includes generating a signal and varying a first and second impedance to control the rise and fall time and average level of the signal to produce an output signal, wherein a plurality of voltage levels are modified. Then, varying a first reference current to produce a second reference current that provides a source for a plurality of currents, wherein the plurality of currents includes a first current, a second current and a third current. In addition, scaling the second reference current producing the first current, second current and third current to correct the plurality of modified voltage levels, wherein errors induced by an external environment and manufacturing tolerances are reduced.

Abstract: The present invention provides a transceiver which does not lose synchronization upon a transition from a non-precoded communication mode to a precoded communication mode and minimizes phase drift. A transceiver unit outputs a signal representing the phase of a received signal, and that possesses a controllable sampling rate. The transceiver is coupled to a phase reference selector and a timing control system. Upon a transition between communication modes, an adaptation period is initiated. The phase reference selector captures the phase estimate immediately prior to termination of the adaptation period, outputting a predetermined phase reference until such termination, at which point the stored phase estimate is outputted. The timing control system minimizes the difference between the phase estimate and the output of the phase reference selector by altering the sampling rate, except during the adaptation period, during which the sampling rate is held constant.