Patents Assigned to Lewis Innovative Technologies
  • Patent number: 9218477
    Abstract: An electronic asymmetric unclonable function applied to an electronic system being evaluated includes an electronic system and an AUF array electronically associated with the electronic system. The AUF array includes a plurality of non-identical cells. Each of the non-identical cells includes a test element representing a characteristic of the electronic system being evaluated and a measurement device evaluating the test element. A comparison unit processes an output of the measurement device to provide a multi-bit output value representing a magnitude of differences.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: December 22, 2015
    Assignee: LEWIS INNOVATIVE TECHNOLOGIES
    Inventors: James M Lewis, Dane R Walther, Paul H Horn
  • Patent number: 9171144
    Abstract: An electronic asymmetric unclonable function applied to an electronic system being evaluated includes an electronic system and an AUF array electronically associated with the electronic system. The AUF array includes a plurality of non-identical cells. Each of the non-identical cells includes a test element representing a characteristic of the electronic system being evaluated and a measurement device evaluating the test element. A comparison unit processes an output of the measurement device to provide a multi-bit output value representing a magnitude of differences.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: October 27, 2015
    Assignee: LEWIS INNOVATIVE TECHNOLOGIES
    Inventors: James M Lewis, Dane R Walther, Paul H Horn
  • Patent number: 8896346
    Abstract: A self-modifying FPGA system includes an FPGA and a configuration memory coupled to the FPGA for providing the FPGA with configuration data including SAFE configuration data and dormant configuration data. The SAFE configuration data is initially loaded to the FPGA and the FPGA is configured to a safe operating mode. Upon a determination to proceed to a next step of self modification, dormant configuration data contained in the configuration memory is loaded into the FPGA and the FPGA is configured to a secure operating mode.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: November 25, 2014
    Assignee: Lewis Innovative Technologies
    Inventors: James M. Lewis, Joey R. Haddock, Dane R. Walther
  • Patent number: 8598890
    Abstract: A system employs physical unclonable functions of an integrated circuit for detecting integrated circuits and protecting products and technology from integrated circuits which have been subject to tampering, stressing and replacement, and counterfeit components. The system includes a sensor detecting a characteristic impedance generated as a result of controlled access to a memory device of the integrated circuit. The characteristic impedance is applied in the creation of a discrimination matrix of values based on electrical interface signals for the integrated circuit. The sensor includes a ring oscillator and associated monitoring components. The ring oscillator is composed of the memory device of the integrated circuit and a sensory circuitry, wherein changes in a frequency generated by the ring oscillator is indicative of changes in circuitry.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: December 3, 2013
    Assignee: Lewis Innovative Technologies
    Inventors: James M. Lewis, Paul H. Horn, Dane R. Walther