Abstract: A high-speed low-noise trans-impedance amplifier (TIA) with fast overdrive recovery is suitable for use in light detection and ranging (LIDAR) receivers.

Abstract: A ripple monitoring circuit may generate information indicative of a failing component in a power supply. At least one input may receive a ripple signal from the power supply that has a ripple component. A quantization circuit may repeatedly quantize the amplitude of the ripple component. A ripple amplitude statistics counter bank may count and store the number of times that different quantized amplitudes or different ranges of quantized amplitudes of the ripple component occurred. A ripple monitoring circuit may generate information about a power supply. At least one input may receive a ripple signal from the power supply that has a ripple component. A ripple measurement circuit may measure a characteristic of the ripple component. A storage circuit may store information about the measurement. A comparison circuit may compare information stored in the storage circuit with a threshold value and indicate when the stored information meets or exceeds this threshold value.

Abstract: A switch mode power supply may utilize a switching signal to control one or more power switches in the switch mode power supply. A switch mode power supply controller may generate and/or control this switching signal. The controller may reduce the peak spectral noise of the switch mode power supply by varying the instantaneous switching frequency at a constant slew rate magnitude that changes sign at random times. The instantaneous switching frequency may be controlled by a signal that is generated by integrating a random bit stream. The stream may repeat at a sub-audio frequency. The integrator may be lossy, so that the output does not wonder off to an arbitrary value. The frequency modulation signal may be filtered by a low pass filter.

Abstract: The stability of a channel in a wireless network is evaluated at a node. Upon transmitting a packet from the node on a network channel, a first counter associated with the channel is incremented. Upon receiving an acknowledgment packet responsive to the transmitted packet, a second counter associated with the channel is incremented. A stability metric for the channel is computed based on values stored in the first and second counters. Additionally, interference on a channel of the network is measured at a node. Upon determining that no packet is received during a predetermined time-period on the channel, a received signal strength (RSS) is measured on the channel at an end of the predetermined time-period. Alternatively, upon determining that a packet is received during the predetermined time-period on the channel, the RSS is measured on the channel following completion of the transmission of the packet on the channel.

Abstract: A flipchip may include: a silicon die having a circuit side with solder bumps and a non-circuit side; a leadframe attached to the solder bumps on the circuit side of the silicon die; a heat spreader attached to the non-circuit side of the silicon die; and encapsulation material encapsulating the silicon die, a portion of the leadframe, and all but one exterior surface of the heat spreader. The leadframe may have NiPdAu plating on the portion that is not encapsulated by the encapsulation material and no plating on the portion that is attached to the solder bumps.

Abstract: One or more Power Sourcing Equipment (PSE) are coupled to points in a network of interconnected nodes. Each node has a first port and a second port. Assume the first port of a first node is receiving DC power from the PSE. The first node, at its second port, then detects an electrical signature from a first port of an adjacent second node. If the proper electrical signature is presented by the adjacent second node, the powered first node closes a switch to pass power between its first port and second port to power the second node via the first port of the second node. All nodes in the network are then sequentially powered up in this manner. If there is a fault between the first node and the second node, the second node will be powered by another node connected to the second port of the second node.

Abstract: The stability of a channel in a wireless network is evaluated at a node. Upon transmitting a packet from the node on a network channel, a first counter associated with the channel is incremented. Upon receiving an acknowledgment packet responsive to the transmitted packet, a second counter associated with the channel is incremented. A stability metric for the channel is computed based on values stored in the first and second counters. Additionally, interference on a channel of the network is measured at a node. Upon determining that no packet is received during a predetermined time-period on the channel, a received signal strength (RSS) is measured on the channel at an end of the predetermined time-period. Alternatively, upon determining that a packet is received during the predetermined time-period on the channel, the RSS is measured on the channel following completion of the transmission of the packet on the channel.

Abstract: A current mode switching regulator circuit and operating method includes a variable duty cycle power switch controller, a voltage feedback loop that provides a feedback signal based on the output voltage, a current feedback loop that provides a current sense signal based on the output current, and an offset circuit having an external signal input and coupled to the current feedback loop. The power switch controller controls the switching regulator circuit to generate an output voltage and an output current. The offset circuit is configured to provide an offset output control signal, independently of the voltage feedback loop, to control the power switch controller so as to vary a duty cycle of the power switch controller based on the current sense signal and an external offset signal applied to the external signal input.

Abstract: Methods and systems of pre-balancing a switched capacitor converter are provided. A first comparator includes a positive input configured to receive a voltage across an output capacitor and a negative input configured to receive a first hysteresis voltage. A second comparator includes a positive input configured to receive a voltage across an input capacitor of the switched capacitor converter and a negative input configured to receive a second hysteresis voltage. A first current source is coupled between the output capacitor and GND and is configured to discharge the output capacitor upon determining that the voltage across the output capacitor is above a tolerance provided by the first hysteresis voltage. A second current source is coupled between the input capacitor and GND and is configured to discharge the input capacitor upon determining that the voltage across the input capacitor is above a tolerance provided by the second hysteresis voltage.

Abstract: In a communications system that conducts differential data via a pair of wires, AC common mode noise is undesirably coupled to the wires in a noisy environment. A hybrid common mode choke (HCMC) attenuates the AC common mode noise while passing the differential data to a PHY. The HCMC includes a CMC (windings with the same polarity) and a differential mode choke (windings with opposite polarities). The CMC attenuates the AC common mode noise, and the DMC passes the attenuated AC common mode noise to termination circuity to eliminate it. Also disclosed is a technique for Kelvin sensing the DC voltage at the pair of wires, in a PoDL system, by detecting the voltage on wires that do not carry DC current, so as to provide a more accurate measurement.

Abstract: A method and system of driving a switched capacitor converter having a plurality of switches. A first driver coupled to a first switch is powered by providing a first reference voltage level VCC to a first supply and a GND reference to a second supply node of the first driver. A second driver coupled to a second switch is powered by providing a unidirectional path between the first supply node of a first driver and the first supply node of the second driver and by keeping OFF the second switch while turning ON the first switch. A third driver coupled to a third switch is powered by providing a unidirectional path between the first supply node of a second driver and the first supply node of the third driver and by keeping OFF the first and third switch while turning ON the second switch.

Abstract: In a communications system that conducts differential data via a pair of wires, AC common mode noise is undesirably coupled to the wires in a noisy environment. A hybrid common mode choke (HCMC) attenuates the AC common mode noise while passing the differential data to a PHY. The HCMC includes a CMC (windings with the same polarity) and a differential mode choke (windings with opposite polarities). The CMC attenuates the AC common mode noise, and the DMC passes the attenuated AC common mode noise to termination circuitry to eliminate it. Also disclosed is a technique for Kelvin sensing the DC voltage at the pair of wires, in a PoDL system, by detecting the voltage on wires that do not carry DC current, so as to provide a more accurate measurement.

Abstract: A technique to eliminate perceptible flickering by LEDs being dimmed by PWM pulses is disclosed. A controllable oscillator controls a switching frequency of a converter for supplying a regulated current or regulated voltage. The converter controls a first switch at a switching frequency. A varying second signal level is generated by a spread spectrum control (SSC) circuit for controlling the oscillator to vary the switching frequency during operation. A PWM dimming circuit generates a string of PWM pulses that control a switch in series with the LEDs. The SSC circuit is synchronized with the PWM pulses to generate the same second signal level at a start of each PWM pulse, such that the switching frequency of the converter is forced to be substantially the same at the start of each PWM pulse while the pulse widths are constant. The repeating driving current waveform eliminates perceptible flicker by the LEDs.

Abstract: In one embodiment, a master device has a first port and a second port and initially applies a DC voltage only to the first port. A plurality of slave devices, each have a third port and a fourth port, are serially connected to the master device in a ring, via conductors, starting at the first port and ending at the second port. The conductors simultaneously carry the DC voltage and differential data. Each slave device, after performing a detection routine, then sequentially applies the DC voltage to the adjacent downstream slave device in a first direction around the ring. If the master does not detect the presence of the DC voltage at its second port, the master device applies the DC voltage to both the first port and the second port to sequentially power up the slave devices in both directions around the ring of slave devices.

Abstract: A hybrid power converter circuit includes a switched-capacitor power converter stage and a pulse-width modulation (PWM) or resonant output circuit coupled to a switching node of the switched-capacitor power converter stage. In particular, the PWM or resonant output circuit can include a transformer having a primary winding and a secondary winding magnetically coupled to each other, and the secondary winding is coupled to the output node of the power converter. The switched-capacitor power converter stage is coupled between the input node of the power converter and the primary winding of the transformer, and includes capacitors and switches configured to connect the capacitors to the input node during a first phase of operation and connect the capacitors to the primary winding of the transformer of the PWM or resonant output circuit during a second phase of operation.

Abstract: In a method performed by a PoE system, a PSE provides data and operating voltage over Ethernet wires to a PD. Before the full PoE voltage is supplied, the PSE generates a low current signal received by the PD. A circuit in the PD, connected across its input terminals, has a characteristic analog response to the PSE signal corresponding to the PD's PoE requirements, such as whether the PD is a Type 1 or Type 2 PD. The circuit may be a certain value capacitor, zener diode, resistor, or other circuit. The PSE may generate a fixed current, fixed voltage, or time varying signal. Upon the PSE sensing the magnitude of the analog signal response at a particular time, the PSE associates the response with the PoE requirements of the PD. The PSE then applies the full PoE voltage in accordance with the PD's PoE requirements.

Abstract: The invention pertains to systems where DC power is supplied by a PSE to a PD, such as over differential data wire pairs. IEEE standards require a minimum current to be drawn from the PD in order for the PSE to continue supplying the DC voltage. If the PD is in a low power mode, the PSE will normally discontinue supplying the DC voltage, which then requires a new detection and classification routine for powering up again. To avoid this, a “maintain power signature” controller provides a periodic current pulse by a current source connected between the PD input and the PD's full bridge rectifier. Any droop in the DC voltage that reverse biases the full bridge rectifier while the PD is in its low power mode will not affect the current pulse, so the PSE continues to supply the DC voltage.

Abstract: In one embodiment, a pass MOSFET is coupled in series between an input voltage and a load, and a bypass capacitor is connected in parallel with the load. In response to a voltage step across the MOSFET, the MOSFET is adaptively controlled to conduct an in-rush current of 2ICL=2IL during the bypass capacitor 12 charging time, where ICL is the capacitive current and IL is the load current. This optimizes the in-rush current to achieve a minimum peak temperature of the MOSFET. In one embodiment, a ramp capacitor connected to the drain of the MOSFET is part of a feedback path that tracks the MOSFET drain voltage to control the gate voltage.

Abstract: A PoDL system includes a PSE connected via a wire pair to a PD, where differential data and DC power are transmitted over the same wire pair. Typically, low voltage/current detection and classification routines are required upon every powering up of the system to allow the PD to convey its PoDL requirements to the PSE. Various techniques are described that simplify or obviate such start-up routines or enable increased flexibility for the PoDL system. Such techniques include: ways to specify a particular PD operating voltage; ways to disable the PD's UVLO circuit during such routines; using opposite polarity voltages for the two routines; using voltage limiters or surge protectors to convey the PoDL information; detecting loop resistance; using a PSE memory to store previous results of the routines; and powering the PD communication circuit using the wire pair while the PD load is powered by an alternate power source.

Abstract: A method and system of providing an active differential resistor. The active differential resistor includes a diode having a first node and a second node. There is a capacitor coupled in series between the first node of the diode and an input of the active differential resistor. There is a current source coupled across the first node and the second node of the diode and configured to forward bias the diode such that a Johnson-Nyquist noise of the active differential resistor is replaced by a shot noise.