Abstract: A tunable and trimmable analog filter may include a tunable analog filter and a trimming circuit. The tunable analog filter may set the frequency of a characteristic of the tunable analog filter based on a digital tuning signal that is indicative of a desired frequency of the characteristic. However, the tunable analog filter may contain components having values that deviate from specified values due to variations during manufacture of the tunable analog filter. The value deviations can cause the frequency of the characteristic not to precisely match the frequency indicated by the digital tuning signal. The trimming circuit may include a non-volatile memory that contains data. The trimming circuit may receive tuning information indicative of a desired frequency for the characteristic of the tunable analog filter.

Abstract: A system for and method of providing a signal proportional to the absolute temperature of a semiconductor junction is provided. The system comprises: a preprocessing stage configured and arranged so as to process a signal from the semiconductor junction so as to produce a preprocessed signal including a resistance error term; and a temperature to voltage converter stage for converting the preprocessed signal to a voltage proportional to absolute temperature representing the absolute temperature of the semiconductor junction; wherein the system is configured and arranged so as to remove the resistance error term so as to produce a resistance error free signal representative of the semiconductor junction temperature.

Abstract: A poly-phase filter receives inphase input signals I and ? and quadrature input signals Q and Q, and provides inphase output signals Iout and Iout and quadrature output signals Qout and Qout. The capacitance of each variable capacitor connected to the terminals providing inphase output signals Iout and Iout is and the capacitance of each variable capacitor connected to the terminals providing quadrature output signals Qout and Qout, are different in value, and preferably by twice a predetermined value. This is because adjustment to the capacitance values may be made to each set of variable capacitors by the predetermined value.

Abstract: A device reduces its energy consumption using a relatively lower frequency and lower power secondary oscillator to maintain timing information when a higher frequency and higher power primary oscillator is inactivated. The secondary oscillator maintains timing information at a higher resolution than the period of the oscillator, so as to conserve synchronization when the higher frequency, higher power primary oscillator is inactivated. In some embodiments, a microsequencer is programmably configured to control an integrated radio receiver and transmitter using less power than an associated microprocessor would use to perform the same functions. In other embodiments, flexible event timing facilitates the merging of wake-up events to reduce the energy consumed by wake-up operations in the device.

Abstract: A forward converter has a primary side containing a PWM controller for controlling switching of a power switch and has a secondary side coupled to the primary side via a transformer. The secondary side includes a forward transistor and a catch transistor. A secondary side switch controller controls switching of the forward transistor and the catch transistor without communication from the primary side. The secondary side switch controller detects the rising and falling of the voltages at the ends of the secondary winding to control the switching of the forward and catch transistors. A delay locked loop (DLL) is provided in the secondary side switch controller that turns on the catch transistor when the power switch is turned off and turns off the catch transistor at a predetermined time before the power switch is turned on. A separate circuit controls the catch transistor during a discontinuous mode.

Abstract: A method and an ADC circuit use multiple SD modulations on an analog value and apply digital post-processing of the pulse density modulation (PDM) streams from the SD modulations obtaining a higher resolution in the digital output value for a given oversampling ratio. SD ADC does not face the constraint of conversion time doubling for each additional bit of resolution. In one implementation, an SD ADC includes conversions in SD phase and resolution-boosting phase. During SD phase, MSBs of the digital output value are generated from the sampled analog value using a first SD conversion. At the end of SD phase, the sampled analog value is reduced to “residual quantization error,” which remains in a capacitor of an integrator of SD ADC. In resolution-boosting phase, the LSBs of the digital output value are generated from residual quantization error using a second SD conversion that provides at least the LSBs.

Abstract: A DC/DC converter configurable for operating as a multiphase DC/DC. A controller produces a master drive signal for controlling a primary power switch to produce the output DC signal at a desired level. Multiple secondary power stages are coupled between the input and the output nodes for producing an output DC signal. Each of the multiple secondary power stages has at least one secondary power switch responsive to the input DC signal for producing the output DC signal. An expander system configures the DC/DC converter for operation in a multiphase DC/DC conversion mode. The expander system is responsive to the master drive signal for producing multiple slave drive signals respectively supplied to the multiple secondary power stages for controlling secondary power switches. The slave drive signals have phases shifted with respect to the master drive signal and with respect to each other.

Abstract: An LED driver uses a positive-to-floating boost converter topology to generate a negative voltage ?Vee relative to ground. The converter receives an input voltage. Vin from a power supply. One end of an output inductor is coupled to ground, and the other end of the inductor is coupled between a highside switch and a low side switch. The bottom terminal of the lowside switch generates ?Vee. The anode end of an LED string is coupled to Vin and the cathode end is coupled to ?Vee. The converter detects the LED current and regulates the switching duty cycle so that the LED current is equal to a target current. This is more efficient than coupling the anode end of an LED string to ground and the cathode end to ?Vee. A conventional buck controller IC may be used.

Abstract: A linear regulator contains an additional AC-coupled feedback loop between the output of the error amplifier and the base of the pass transistor that increases the frequency of the pole at the output of the error amplifier at light load currents to at least partially offset the decreased frequency of the output pole at the lighter load currents. Thus, a desired phase margin is preserved. The AC-coupled feedback loop includes a bipolar feedback transistor connected in parallel with the pass transistor. A resistor is connected to the emitter of the feedback transistor to reduce the relative gain of the feedback transistor above light load currents. A feedback capacitor Cfb is connected between the collector of the feedback transistor and the output of the error amplifier. The negative AC feedback increases the pole frequency at the output of the error amplifier and the base of the pass transistor.

Abstract: In a method for controlling a current regulator for dimming an LED load, a dimming signal has a duty cycle that controls the LED ON-time and LED OFF time at a fixed frequency. The regulator is controlled by the dimming signal to only supply current to the LED load during the LED ON-time. The regulator includes an inductor. The inductor current at the end of an ON-time is detected and its value is stored. During the OFF-time, the inductor is pre-charged to the current level matching the stored value, while the regulator's feedback loop is frozen during the OFF-time to not change its feedback control signal. Upon the next ON-time, the regulator begins supplying current to the LED load with the pre-charged inductor current, so there is no initial decrease in the delivered LED current. Therefore, the current pulse magnitudes are constant even with very low duty cycles.

Abstract: An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.

Abstract: In a method for controlling a current regulator for dimming an LED load, a dimming signal has a duty cycle that controls the LED ON-time and LED OFF time at a fixed frequency. The regulator is controlled by the dimming signal to only supply current to the LED load during the LED ON-time. The regulator includes an inductor. The inductor current at the end of an ON-time is detected and its value is stored. During the OFF-time, the inductor is pre-charged to the current level matching the stored value, while the regulator's feedback loop is frozen during the OFF-time to not change its feedback control signal. Upon the next ON-time, the regulator begins supplying current to the LED load with the pre-charged inductor current, so there is no initial decrease in the delivered LED current. Therefore, the current pulse magnitudes are constant even with very low duty cycles.

Abstract: A circuit and method for wirelessly coupling an electrical energy between an electrical energy source and at least one load is provided. The circuit comprises a primary unit and at least one secondary unit. The primary unit includes an input node for receiving an input voltage produced by the energy source; a transmitter circuit including a transmitter coil configured to generate an electromagnetic field; and a regulator. The regulator is configured to sense a current consumption of the primary unit, determine a gradient of the current consumption with respect to different input voltages, and determine an optimal input voltage based on the gradient. The at least one secondary unit comprises a receiver circuit and a load. The receiver unit includes a coil that wirelessly and inductively couples with the electromagnetic field of the primary unit to receive power therefrom. The receiver unit further includes a regulator circuit configured to provide a constant power to an output node.

Abstract: A system for combining power to a load in a Powered Device (PD) using Power Over Ethernet (PoE) receives power from a first channel and power from a second channel, via four pairs of wires. A MOSFET bridge for each channel is initially disabled. A bridge controller IC simultaneously senses all the voltages and controls the bridge MOSFETs. The bridge controller IC also contains a first PoE handshaking circuit. A second PoE handshaking circuit is external to the bridge controller IC and operates independently. The body diodes in the MOSFET bridge initially couple the first channel to the second PoE handshaking circuit while isolating the second channel. The second handshaking circuit then couples the first channel to the load. The first handshaking circuit then carries out a PoE handshaking routine for the second channel. Ultimately, the bridge controller controls the bridge MOSFETs to couple both channels to the load.

Abstract: A technique for combining power to a single load from multiple power supplies using power over Ethernet (PoE) is disclosed. Each power supply is coupled to associated power sourcing equipment (PSE) providing PoE, and each PSE has a current limit. The power supplies supply approximately the same voltage, but the output voltages are typically not exactly equal. All the power supplies are connected via diodes to a common load terminal. The power supply outputting the highest voltage first supplies power to the load terminal, since only its diode is forward biased, until a PoE current limit is reached. Then its duty cycle is limited. The load terminal voltage is then inherently lowered to cause the diode of the power supply with the next highest output voltage to connect it to the load to supply additional power to the load as the first power supply continues to supply its limited current.

Abstract: An isolated flyback converter having temperature compensation (TC) uses primary side sensing and an output diode, the output diode having a variable voltage drop related to its temperature. A feedback voltage VFB, proportional to the output voltage VOUT, in a feedback loop is compared to a fixed reference voltage VREF for setting a duty cycle of a power switch, wherein VFB is caused to approximately equal VREF. A TC circuit has a voltage source configured to generate a proportional-to-absolute-temperature voltage VPTAT, wherein VPTAT is at approximately VREF at a calibration temperature T0 and rises as a temperature exceeds T0. The voltage source is connected to the VFB node via a TC resistor RTC, so that at T0 no current flows through RTC. Therefore, the selection of the optimal RTC does not affect the selection of a scaling resistance for generating VFB. The current through RTC at elevated temperatures compensates VOUT.

Abstract: A bootstrapped switch circuit capable of operating at input signals from far below the negative supply rail to far beyond the positive supply rail may include (a) a switch having a first terminal coupled to an input terminal, a second terminal coupled to an output terminal, and a control terminal; (b) a charge pump coupled to one or more clock signals and isolated from a timing circuit via a first capacitor and a second capacitor, the charge pump generating an output voltage; and (c) a logic circuit coupled to one or more clock signals and isolated from the timing control circuit via a third capacitor and a fourth capacitor, wherein the logic circuit provides a control signal to the control terminal of the switch that is derived from the output voltage of the charge pump.

Abstract: An amplifier circuit has a voltage input terminal, for receiving Vin, and a voltage output terminal, for outputting Vout. A feedback circuit controls Vout to match Vin. A differential input stage receives Vin and Vout and generates a first output signal. An output stage comprises a pull down circuit for Vout. A main MOSFET is controlled by the first output signal to pull down Vout to match Vin when Vout is above a threshold voltage Vtrans. An auxiliary MOSFET, in parallel with the main MOSFET, is controlled by the first output signal to pull down Vout to match Vin when Vout is below Vtrans. The main MOSFET is turned substantially off when Vout is below Vtrans. A headroom generator coupled between the Vout terminal and a drain of the auxiliary MOSFET allows the auxiliary MOSFET to operate in its active region and pull Vout to ground.

Abstract: In a method for controlling a current regulator for dimming an LED load, an adjustable delay circuit generates a delayed second dimming signal from an original first dimming signal. The second dimming signal has a duty cycle that controls the LED ON-time and LED OFF time at a fixed frequency. An ON-time pulse of the first dimming signal starts a pre-charging of the regulator's inductor to approximately the inductor current previously detected at the end of the previous ON-time of the LEDs. The pre-charging ends at the leading edge of the delayed ON-time pulse of the second dimming signal. The second dimming signal controls the regulator to only supply current to the LED load during the LED ON-time. The delay time is adjusted by a feedback loop. Therefore, the current pulse magnitudes applied to the LED load are constant at every duty cycle even with very low duty cycles.

Abstract: A circuit for providing connection between a first node at a first voltage and a second node at a second voltage. The circuit has a first inductive element having a first terminal coupled to the first node, a first switching element coupled between a second terminal of the first inductive element and the second node, a second inductive element having a first terminal configured for receiving current from the second terminal of the first inductive element, and having a second terminal coupled to a third node, and a second switching element coupled between the first terminal of the second inductive element and the second node. The first and second switching elements are configured for providing alternating current flow paths between the first node and the second node.