Abstract: The invention relates to the protection of devices in a monolithic chip fabricated from an epitaxial wafer, such as a wafer for a Group III-V compound semiconductor or a wafer for a Group IV compound semiconductor. Devices fabricated from Group III-V compound semiconductors offer higher speed and better isolation than comparable devices from silicon semiconductors. Semiconductor devices can be permanently damaged when exposed to an undesired voltage transient such as electrostatic discharge (ESD). However, conventional techniques developed for silicon devices are not compatible with processing techniques for Group III-V compound semiconductors, such as gallium arsenide (GaAs). Embodiments of the invention advantageously include transient voltage protection circuits that are relatively efficiently and reliably manufactured to protect sensitive devices from undesired voltage transients.

Abstract: An improved class D power amplifier is disclosed. Instead of using prior art triangle waves, a ramp signal having a first state of about 90% or greater is used and a second state for the remainder of the cycle. Further, the amplifier includes flip-flops and amplifers with hysteresis to reduce switching noise. Also, level shifting circuitry is provided for shifting the level of the input signal in response to both DC and AC variations in the power supply and to provide power supply rejection. Still further, multiple channels may be used with all of the channels synchronized to the same timing source.

Abstract: A monolithic electronic circuit breaker having an input terminal, an output terminal, and a controllable impedance connected between the input and output terminals. A current sensor generates a current magnitude signal indicative of the current flowing between the input and output terminals. In one embodiment, an over-current circuit generates an over-current signal when the current magnitude signal exceeds a threshold. In response to at least a first occurrence of the over-current signal, a control circuit controls the controllable impedance so as to reduce current through the controllable impedance for a period of time, and then automatically increase current through the controllable impedance. Further, in response to an N.sup.th (N>1) occurrence of the over-current signal, the control circuit controls the controllable impedance so as to reduce current through the controllable impedance and does not thereafter automatically increase current through the controllable impedance.

Abstract: A control circuit for synchronous switching power supplies employing semi-soft switching during turn off and precedent switching during turn on. During turn off, an output voltage is compared to a reference voltage to turn on a synchronous switch after a primary switch is turned off. During turn on, a timing voltage ramp triggers the turn off of the synchronous switch prior to the turn on of the primary switch.

Abstract: A controllable active terminator for a computer bus providing low power, small size, switchable termination of a computer bus having a plurality of conductors. The active terminator includes a voltage reference circuit, an enable circuit, a buffer amplifier, and a plurality of output cells. The voltage reference circuit includes a power down circuit which turns the voltage reference circuit off, using the same control signal which also disconnects the termination resistors and output transistors of the output cells. The terminator uses FET technology to produce a low-power, small size, controllable terminator having stable and reliable operating characteristics. The amplifiers used in the active terminator comprise CMOS devices and thus are relatively small and consume relatively low power. When enabled, the voltage reference circuit is used to establish a reference voltage for the linear operation of the output transistors in the output cell. The output current is supplied by terminator power.

Abstract: A voltage regulator for use in controllable bus terminators providing a source and a sink to a regulated output without clamping circuitry is disclosed. The regulator maintains a voltage at a node by sourcing current into the node when a cable line sinks current from the node and sinking current from the node when a cable line sources current into the node. By avoiding the use of clamping circuitry, a voltage deadband between the regulator output voltage and the clamp circuit voltage is avoided.

Abstract: A floating current mirror circuit is disclosed which achieves high open loop gain without additional voltage gain stages leading to frequency compensation and increased power dissipation. The output of the circuit has only a first pole and is designed to be coupled to a second current source, a base coupled to the first terminal of the diode, and an emitter coupled to the floating node. A second bipolar transistor has a base coupled to the collector of the first transistor, and emitter coupled to the floating node.

Abstract: A bi-mode circuit for driving an output load selectively couples the output load to a supply voltage source or to a low discharge voltage source such as ground using switches which are controlled by an input buffer in response to an input signal. A high input signal closes a first switch to provide a biasing current to first and second current amplifiers to turn on a first output transistor which couples the output load to the low reference voltage to discharge the output load. Conversely, a low input signal closes a second switch to provide the biasing current to a third current amplifier to turn on a second output transistor which couples the output load to the supply voltage source. When the input signal becomes high, rapid pulldown of a capacitive output load is achieved using a high internal pre-drive current provided by the first and second current amplifiers, in a first mode of operation.

Abstract: An improved output stage for a CMOS circuit is disclosed. In particular, the circuit drives both output transistors of a push-pull output in class AB operation for efficient power usage with low noise and distortion with a minimal number of components.

Abstract: A pulse detection and conditioning circuit senses and conditions commutation pulses produced by a DC permanent magnet motor to determine motor position. The pulses are sensed using a resistor coupled in series with the motor, so that motor current and the included pulses are continuously sensed, even during motor braking. The serially coupled resistor also provides for sensing and conditioning of pulses of both polarities produced by bi-directional operation of the motor. The pulse detecting and conditioning is performed by circuitry which performs amplitude qualification as well as frequency filtering to effectively detect valid commutation pulses to the exclusion of noise and other unwanted signals. Capacitors coupled to the motor and internal capacitors provide the frequency filtering, while the amplitude qualification is provided by a balanced differential gain stage coupled through an adjustable differential gain stage with adjustable gain to a unity gain comparator.

Abstract: A power supply controller includes a comparator for providing a regulated voltage when an input voltage exceeds a reference voltage, so that a reference voltage is provided to drive a load discharge circuit. When the input voltage is less than the reference voltage, such as during a startup or sleep mode of operation of the controller, the load discharge circuit is driven by an output pulldown circuit so as to maintain minimum functions within the integrated circuit of the controller including turnoff of an external MOSFET. The output pulldown circuit senses the resulting absence of the regulated voltage using a first transistor coupled to be biased into nonconduction when the regulated voltage is not provided. This biases a second transistor into conduction to maintain a transistor within the load discharge circuit conductive. In this manner, the output powers its own operation, including the pulldown thereof.

Abstract: A voltage reference circuit includes a band-gap reference circuit for providing a reference voltage and having breakpoint compensation to adjust the temperature coefficient of the reference voltage as a function of temperature. A thermal limit transistor biased by a voltage having a positive temperature coefficient begins conducting when the operating temperature reaches a predetermined value to provide a compensation current. The compensation current is added to the collector current flowing into one of a pair of transistors within the band-gap reference circuit, and a current controlled current source responds to an increase in collector current in the other one of the pair of transistors by making the collector currents flowing into both transistors equal. This increases the voltage drop across a pair of resistors to increase a band-gap voltage across a portion of an output divider network, to in turn increase the reference voltage provided across the entire divider network.