Abstract: Disclosed is a flipchip scheme where power and ground bumps are arranged in a striped configuration. Specifically, there are a plurality of lines of power bumps, and a plurality of lines of ground bumps. Each line of power bumps is interconnected by a mesh core power bus, and each line of ground bumps is interconnected by a mesh core ground bus. The busses are shorted across the bumps without having to use metal tab extensions. This arrangement provides that: signal routing can be provided between the lines of bumps; and/or the mesh core power busses can be provided as being wider in order to provide improved power mesh performance and/or in order to reduce or eliminate the metal required on the second top-most metal layer.

Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the ground plane used to ground the low speed circuitry of the package.

Abstract: Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.

Abstract: An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserved as fixed layers. By coupling a maximum of two layout cells together, a single-port or dual-port memory cell is realized. Likewise, by interconnecting transistors within a single cell or transistors among two or more cells, a logic device is realized. Within each cell, the bit lines are arranged on a layer separate from the wordlines, and extend orthogonal to each other.

Abstract: Provided are methods and composition for forming a multi-layer isolation structure on an integrated circuit substrate. A process can include selecting a lower dielectric material for the lower dielectric layer and selecting an upper dielectric material for the upper dielectric layer. A range of effective dielectric constants that correspond to the thicknesses the lower and upper dielectric materials are selected. A range of thicknesses for each of the lower and upper dielectric layers are determined from a range of acceptable dielectric constants using information indicating an effective dielectric constant corresponding to thicknesses of the materials for both the lower upper dielectric layers, enabling the formation of the multi-layer isolation structure.

Abstract: Systems and methods herein provide for load balancing Fibre Channel traffic. In this regard, a Fibre Channel load balancer may be operable to monitor Fibre Channel paths coupled to a host bus adapter and determine the speeds of the Fibre Channel ports within the Fibre Channel paths. The Fiber Channel load balancer may also be operable to determine certain characteristics of the Fibre Channel traffic being passed over the Fibre Channel paths. For example, a load balancer may determine Fibre Channel traffic sizes of pending requests and, based in part on the traffic sizes and operable normalized speeds of the Fibre Channel ports, adaptively route the pending original traffic across the Fibre Channel ports.

Abstract: An integrated circuit package includes a package substrate, a die attach pad formed on the package substrate for securing a die to the package substrate, a ground bonding ring formed on the package substrate for attaching core and I/O ground bond wires between the die and the package substrate, and a first plurality of bond fingers formed immediately adjacent to the ground bonding ring for attaching a first set of I/O signal bond wires between the package substrate and the die.

Abstract: A latch-based integrated circuit random access memory having selectable bit write capability that is less susceptible to disturbing data stored in unselected bits during write operations by utilizing an inhibit signal to block writing of the unselected bits.

Abstract: An integrated circuit structure for distributing power to one or more standard cells in an integrated circuit includes a first plurality of standard cells and a power mesh power connection structure coupled to the cells. Each of the standard cells includes first and second power rails adapted for connection to a voltage supply and a voltage return, respectively, of the standard cells. Each standard cell in a subset of the standard cells is arranged in direct abutment with at least two other standard cells, and at least first and second end cells are arranged in direct abutment with at least one other standard cell of the first plurality of standard cells. The power mesh power connection structure includes a plurality of conductive elements formed in a plurality of different conductive layers in the integrated circuit.

Abstract: The present invention is directed to an apparatus capable of dual porting a serial advanced technology attachment (SATA) disk drive in a fault tolerant communication system, such as fiber channel. The dual porting apparatus includes two idle regenerators coupled to two serial master devices, a synchronization logic capable of synchronizing the communications between one of the idle regenerators and a third idle regenerator coupled to the SATA disk drive. Furthermore the dual porting apparatus may include an auto detector capable of enabling either of the first two idle regenerators, thus effectively switching between the two.

Abstract: A method and apparatus is provided for determining thickness of films or layers during chemical-mechanical planarization/polishing (CMP) of a semiconductor substrate or wafer in situ. The method may be used to determine end-point during CMP especially of oxide films deposited on the substrate or wafer. In one embodiment, the method includes: a) capturing images of the surface of the substrate using high speed imaging; b) performing pattern recognition on the captured images; c) selecting one of the captured images based on the pattern recognition; and d) converting the selected image into a thickness measurement. In one form, the high speed imaging comprises a high speed camera, while in another form, the high speed imaging comprises a conventional camera and a laser pulse or flash tube. In yet another embodiment, reflective laser interference patterns of the substrate are captured and analyzed for interference pattern changes that can signal a practical end-point.

Abstract: Disclosed is a method of improving a synthesized circuit design comprising searching the synthesized circuit design for a first instance of a first pattern of gates. The first instance is removed from the synthesized circuit design. The first instance is replaced with a non-synthesized cell. A method of altering a multiplexer implementation comprises receiving a netlist that describes a synthesized logic circuit design. Parsing the netlist to detect a first instance of a first pattern of gates that implements a first multiplexer. The first instance is replaced in the netlist with a technology implementation of the first multiplexer.

Abstract: The present invention is directed to an apparatus for reducing and constraining EMI (electronic magnetic radiation) emissions without affecting the internals of data storage system components. A baffle is attached to the exterior of the housing of a data storage system component by baffle mounts. The baffle is operable between a closed position, where the baffle blocks EMI emitted by connectors on the data storage system component, and an open position, where the connectors are not blocked allowing for servicing and cable management. The baffle may comprise an EMI absorbing material and be tuned to meet specific EMI requirements. The baffle mounts offsets the baffle from the data storage system component and the baffle includes a number of holes to allow airflow. The adjustable EMI baffling apparatus does not interfere with other mounted components while the data storage system component is mounted in a cabinet.

Abstract: An integrated circuit is provided that includes an execution engine and a memory controller. The execution engine is clocked at a first rate and the memory controller is clocked at a second rate that is less than the first rate. Pins on the integrated circuit can transfer data to and from the integrated circuit on both the rising and falling edges of a second clock transitioning at the second clock rate. The integrated circuit is preferably packaged using a lead frame and wire bonds extending from pads on the integrated circuit to corresponding leads. The leads are secured to trace conductors on a surface of a printed circuit board. The board contains no more than two conductive layers separated by a dielectric layer.

Abstract: Methods and apparatus to enhance performance of Serial Advanced Technology Attachment (SATA) disk drives in Serial-Attached Small Computer System Interface (SAS) domains are described. In one embodiment, a data packets and/or commands communicated in accordance with SAS protocol may be converted into SATA protocol. Other embodiments are also described.

Abstract: A comparator receives a first read of voltage differentials from a series of bit cells, compares the first read to a positive voltage offset of a given magnitude, and set bits in a first bit stream to values that are dependent upon whether the voltage differential from a given bit cell is greater than the positive voltage offset. The first bit stream is then stored in a first register. The comparator also receives a second read of the voltage differentials from the series of bit cells, compares the second read to a negative voltage offset of the given magnitude, and sets bits in a second bit stream to values that are dependent upon whether the voltage differential from a given bit cell is greater than the positive voltage offset. The second bit stream is stored in a second register. The comparator then compares the first bit stream to the second bit stream, and set bits in a mask string dependent upon whether the bits in a given position of the first bit stream and the second bit stream are identical.

Abstract: A clock pulse controller includes a test clock pulse input for receiving test clock pulses. A scan enable input receives a scan enable signal having a first state and a second state. A trigger pulse input receives a trigger pulse. A clock pulse output generates a launch clock pulse and a capture clock pulse from the test clock pulses immediately after receiving a predetermined number of the test clock pulses immediately following the trigger pulse. A delayed scan enable output generates a delayed scan enable signal that transitions from the first state to the second state between a leading edge of the launch clock pulse and a leading edge of the capture clock pulse.

Abstract: In some embodiments, a method for managing embedded devices may include one or more of the following steps: (a) loading an embedded web server module, (b) loading a first webpage when loading a first embedded module, (c) replacing the first webpage with a second webpage when a second embedded module is loaded or when a failure is detected by the first embedded module, (d) loading a boot loader module, (e) interacting with the computer system to correct the failure condition, (f) loading an embedded operating system module, and (g) loading a third webpage when loading a RAID application module.

Abstract: Disclosed is a flipchip scheme where power and ground bumps are arranged in a striped configuration. Specifically, there are a plurality of lines of power bumps, and a plurality of lines of ground bumps. Each line of power bumps is interconnected by a mesh core power bus, and each line of ground bumps is interconnected by a mesh core ground bus. The busses are shorted across the bumps without having to use metal tab extensions. This arrangement provides that: signal routing can be provided between the lines of bumps; and/or the mesh core power busses can be provided as being wider in order to provide improved power mesh performance and/or in order to reduce or eliminate the metal required on the second top-most metal layer.

Abstract: A method and apparatus are disclosed in a data processing system for dynamically selecting one of multiple different I/O firmware images for booting a particular I/O controller that is included in the data processing system. Multiple different I/O firmware images are provided. A configuration of the I/O controller is determined. One of the I/O firmware images is identified that supports the configuration of the particular I/O controller. The identified I/O firmware image is then dynamically selected for booting said I/O controller.