Abstract: A method and apparatus for low voltage conversion and energy storage uses a charge pump array including a first set of capacitors in parallel with a second set of capacitors and switches for selectively coupling the first and second set of capacitors to a variable input DC voltage. A data processor programmably controls one or more of the switches to couple the first and second set of capacitors to the variable input DC voltage for a variable first time period during which the input DC voltage charges the first and second set of capacitors to a DC voltage level. An energy storage device is switchably coupled to an output of the charge pump array.

Abstract: A method and apparatus for low voltage conversion and energy storage uses a charge pump array including a first set of capacitors in parallel with a second set of capacitors and switches for selectively coupling the first and second set of capacitors to a variable input DC voltage. A data processor programmably controls one or more of the switches to couple the first and second set of capacitors to the variable input DC voltage for a variable first time period during which the input DC voltage charges the first and second set of capacitors to a DC voltage level. An energy storage device is switchably coupled to an output of the charge pump array.

Abstract: According to one embodiment, the present invention includes a method for numerically encoding and representing data that includes providing a representation of data and separating the representation into a scale header and an additional precision packet. Separating the representation includes identifying the location of the highest-order non-zero bit and encoding the location of the highest-order non-zero bit to form the scale header. The balance of the bits following the highest-order non-zero bit, or a truncated set of these bits, is encoded to form the additional precision packet, and a matched representation space (MRS) representation is composed of the paired data structures of a scale header and a corresponding additional precision packet, if any.

Abstract: A hardware-facilitated secure software execution environment provides protection of both program instructions and data against unauthorized access and/or execution to maintain confidentiality and integrity of the software or the data during distribution, in external memories, and during execution. The secure computing environment is achieved by using a hardware-based security method and apparatus to provide protection against software privacy and tampering. A Harvard architecture CPU core is instantiated on the same silicon chip along with encryption management unit (EMU) circuitry and secure key management unit (SKU) circuitry. Credential information acquired from one or more sources is combined by the SKU circuitry to generate one or more security keys provided to the EMU for use in decrypting encrypted program instructions and/or data that is obtained from a non-secure, off-chip source such as an external RAM, an information storage device or other network source.