Abstract: A memory device comprises a memory array, a status register coupled with the memory array, and a security register coupled with the memory array and the status register. The memory array contains a number of memory blocks configured to have independent access control. The status register includes at least one protection bit indicative of a write-protection status of at least one corresponding block of the memory blocks that corresponds to the protection bit. The security register includes at least one register-protection bit. The register-protection bit is programmable to a memory-protection state for preventing a state change of at least the protection bit of the status register. The register-protection bit is configured to remain in the memory-protection state until the resetting of the memory device.

Abstract: A memory device having at least one multi-level memory cell is disclosed, and each multi-level memory cell configured to store n multiple bits, where n is an integer, wherein the multiple bits are stored in a charge storage layer trapping charge carriers injected by application of a voltage to set or reset a threshold voltage Vt of the memory cell to one of 2n levels. Each memory cell may be programmed to one of 2n multiple levels, wherein each level represents n multiple bits.

Abstract: A memory device comprises a memory array of memory cells for storing data and an information array of information cells for storing operating information. The information array is coupled to the memory array so that the information array and the memory array share the same data path circuitry for reading, erase or programming operations. A power-on control circuit controls the operation of the information array.