Abstract: Techniques are disclosed for performing topologically planar routing of System in Packages (SiPs). A routing graph can be represented by a particle-insertion-based constraint Delaunay triangulation (PCDT) and its dual. A dynamic search routing may be performed using a DS* routing algorithm to determine the shortest path on the dual graph between a start point and an end point. Based on a dynamic pushing technique, net ordering problems may be solved. A first wire can be topologically routed. Dynamic search routing of a second wire may be performed. The first wire may be pushed or detoured in response to the dynamic searching routing of a second wire.

Abstract: A statistical on-chip variation approach to timing analysis permits the automated or semi-automated selection of design-specific margins without requiring complex statistical libraries. By separately addressing the impact of random and systematic variations on timing, a design-specific margin can be obtained and used in downstream OCV analysis. In addition, where statistical libraries are available for some portions of a design, these can be incrementally included in the timing analysis to obtain more accurate results.

Abstract: Electronic Design Automation tools are used to aid in the design and verification of integrated circuits. As part of the verification process, circuit designs are analyzed with respect to their timing performance. Timing analysis is susceptible to variation in circuit components due to fabrication process variation. Process variation is introduced as worst-case conditions or statistical probabilities. More accurate process variation is modeled by for timing sensitivity with Parametric Elmore Delay. Parametric Elmore Delay introduces effects on circuit components as parameters in the conventional Elmore Delay definition to model fabrication process variation in the timing analysis. Delay variance demonstrates sensitivities to process and design factors. Parametric timing analysis is used to anticipate fabrication yield and identify potential improvements in the design or fabrication process.

Abstract: A power optimization method of deriving gated circuitry in an integrated circuit (IC) is provided. A design description of the IC is received and analyzed. A state machine is identified based on the analysis. One or more candidate blocks are determined to be capable of being disabled. At least one of the candidate blocks is selected based on one or more states of the state machine. A gating circuit is inserted for gating the selected candidate block(s). In another embodiment of power optimization, one or more state machines are identified and a synthesized netlist is generated. One or more candidate blocks in the synthesized netlist are determined to be capable of being disabled. At least one of the candidate blocks is selected based on one or more states in the state machine, and a gating circuit is inserted for gating the selected candidate block(s).

Abstract: A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design is provided. A block in the synthesized netlist is identified as an idle candidate block. Sub-blocks on the chip are clustered into a cluster. For the cluster, a clock gating structure optimized for power savings is determined, based on the idle candidate block. One or more inflexible clock gates are inserted in the netlist according to the clock gate structure.

Abstract: Techniques in which an optimal set of clock gating elements is determined for a selected circuit design. Those clock gating elements are coupled to selected flip-flops, with the effect that those selected flip-flops will consume less dynamic power during operation of the logic circuit. The selected set of clock gating elements provides an optimal savings in overall power consumption after modification of that selected circuit design.

Abstract: A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.

Abstract: Methods for optimizing design parameters of a circuit are disclosed. In one aspect, an optimization problem includes one or more performance specifications that represent an exponent of a design parameter to be optimized. Various parameters of passive and active circuit devices may be efficiently and accurately optimized as a result. In another aspect, linear performance specifications are included for accurately calculating voltages. In yet other aspects of the invention, three special types of convex optimization problems are disclosed for enabling the above use of exponents of design parameters which provide efficient and accurate calculations of a virtually unlimited array of circuit parameters and performance characteristics.

Abstract: Methods for optimizing design parameters of a circuit are disclosed. In one aspect, an optimization problem includes one or more performance specifications that represent an exponent of a design parameter to be optimized. Various parameters of passive and active circuit devices may be efficiently and accurately optimized as a result. In another aspect, linear performance specifications are included for accurately calculating voltages. In yet other aspects of the invention, three special types of convex optimization problems are disclosed for enabling the above use of exponents of design parameters which provide efficient and accurate calculations of a virtually unlimited array of circuit parameters and performance characteristics.

Abstract: A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.

Abstract: A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design is provided. A block in the synthesized netlist is identified as an idle candidate block. Sub-blocks on the chip are clustered into a cluster. For the cluster, a clock gating structure optimized for power savings is determined, based on the idle candidate block. One or more inflexible clock gates are inserted in the netlist according to the clock gate structure.

Abstract: Methods for optimizing design parameters of a circuit are disclosed. In one aspect, an optimization problem includes one or more performance specifications that represent an exponent of a design parameter to be optimized. Various parameters of passive and active circuit devices may be efficiently and accurately optimized as a result. In another aspect, linear performance specifications are included for accurately calculating voltages. In yet other aspects of the invention, three special types of convex optimization problems are disclosed for enabling the above use of exponents of design parameters which provide efficient and accurate calculations of a virtually unlimited array of circuit parameters and performance characteristics.

Abstract: A system and a method are disclosed for circuit analysis. A circuit modeling system calculates sensitivities of gates for statistical static timing analysis of a circuit. Timing distribution sensitivities of gates and correlations between the sensitivities are determined. A Monte Carlo simulation is run using the sensitivities to determine timing distribution of paths and determine probabilities of paths being the critical path. Aggregate sensitivities for cells are also determined.

Abstract: A method for generating a layout for an analog circuit design is provided. The method includes tracing a signal flow through a circuit netlist, and partitioning the circuit netlist into a digital portion and an analog portion. A signal flow is defined through the analog portion of the circuit netlist. A system for generating a layout for an analog circuit design is also included.

Abstract: A system and a method are disclosed for integrating the results of lithographic simulation into the physical synthesis process. The effects of lithographic variation are considered when selecting a cell from among a group of cells having equivalent function. Circuit design elements are placed and routed with consideration of the effects of lithographic variation on robustness, timing performance, and leakage current. Cells may be simulated under a variety of conditions and environments and the simulation results stored in a library for efficient lithographically optimized placements.

Abstract: Methods and systems for electronic design automation includes clustering objects into more manageable numbers of objects. Clustering is optionally performed to reduce or minimize interconnections between clusters. Clustering optionally includes multi-level clustering. The clusters, and any unclustered objects, are floorplanned. Floorplanning positions the clusters so as to reduce or minimize the length of interconnections between the clusters. Objects within the clusters are then placed within the area assigned to the corresponding clusters. Placement optionally utilizes placement-based wire load models to accurately predict timing issues. A bottoms-up procedure is optionally performed during clustering and/or floorplanning, whereby area and/or size constraints of clustered objects are taken into account.

Abstract: An instance of a flow definition language for designing an integrated circuit implementation flow. The instance of the flow definition language includes a hierarchical collection of stages for a physical chip design. Relational constraints define the execution order of a plurality of tasks in the hierarchical collection of stages. Parameters customize the plurality of tasks. The relational constraints and parameters are hierarchically defined, such that higher order definitions in the hierarchical collection of stages override lower level definitions of the relational constraints and parameterized knobs.

Abstract: Electronic Design Automation tools are used to aid in the design and verification of integrated circuits. As part of the verification process, circuit designs are analyzed with respect to their timing performance. Timing analysis is susceptible to variation in circuit components due to fabrication process variation. Process variation is introduced as worst-case conditions or statistical probabilities. More accurate process variation is modeled by for timing sensitivity with Parametric Elmore Delay. Parametric Elmore Delay introduces effects on circuit components as parameters in the conventional Elmore Delay definition to model fabrication process variation in the timing analysis. Delay variance demonstrates sensitivities to process and design factors. Parametric timing analysis is used to anticipate fabrication yield and identify potential improvements in the design or fabrication process.

Abstract: A technique to verify, evaluate, and estimate the performance of an integrated circuit is embodied in a computer software program that is executable by a computer system. When simulating performance, scalars for transient performance are determined for strongly couple components. The technique accurately estimates of the performance (e.g., transient delays) of an integrated circuit, and has fast execution times. The technique is applicable to small circuits having relatively few transistors, and especially well suited for integrated circuits having millions of transistors and components. The technique handles the effects of deep-submicron integrated circuit technology.

Abstract: A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.