Abstract: In various embodiments, each possible different instance of a repeated block can be concurrently optimized for timing. Each instance of a repeated block may be treated as a mode, such as a functional mode or testing mode, allowing implementation calculations to be performed simultaneously. Using multimode timing analysis, all instances of a repeated block can be analyzed and optimized simultaneously. Based on the multimode analysis, instances of a repeated block may be implemented identically or substantially similarly, which can reduce costs associated with implementing the same block more than once (e.g., impact to schedule, CPU/memory resources, ECOs).
Type:
Grant
Filed:
May 29, 2008
Date of Patent:
June 28, 2011
Assignee:
Magna Design Automation, Inc.
Inventors:
Robert Swanson, Jacob Avidan, Roger Carpenter