Abstract: A plurality of packets are received by a packet processing device, and the packets are distributed among two or more packet processing node elements for processing of the packets. The packets are assigned to respective packet classes, each class corresponding to a group of packets for which an order in which the packets were received is to be preserved. The packets are queued in respective queues corresponding to the assigned packet classes and according to an order in which the packets were received by the packet processing device. The packet processing node elements issue respective instructions indicative of processing actions to be performed with respect to the packets, and indications of at least some of the processing actions are stored. A processing action with respect to a packet is performed when the packet has reached a head of a queue corresponding to the class associated with the packet.

Abstract: In a method for processing packets, a storage region for a packet is determined based on a queue with which the packet is associated. The storage region includes a committed area reserved for storage of packets associated with the queue, and an area that is shared by multiple queues for packet storage. A first part of the packet is stored in the committed area, a second part is stored in the shared area, and both parts are accounted for. A network device for processing packets comprises a plurality of queues and a storage area including a committed area and a shared area. The network device further comprises a packet queuing engine configured to store a first part of a packet in the committed area, store a second part of the packet in the shared area, and account for the storage of the first and the second parts of the packet.

Abstract: Systems, methods, and computer program products for controlling a plurality of pipelined stages are described. In some implementations, an apparatus is described that includes a pipelined data path including a plurality of adjacent stages, where a stage includes a data store, a valid indicator, and a transfer controller including a state machine having a plurality of states. In some implementations, the stage is configured to send a status indicator different from the valid indicator to the state machine to indicate whether new data is available for processing by the stage in a next cycle, and whether a new data transfer is desired in the next cycle between the stage and the adjacent stage.

Abstract: Methods, circuits, architectures, software and systems for error detection in transmitted data. The method generally includes receiving data and non-data, the data including fixed length data portions, removing non-data; and if the data includes a remainder, adding a zero-pad vector to generate a zero-padded data portion, then checking the data and zero-padded data portions for a transmission error. The circuit generally includes a circuit to detect non-data; a circuit configured to replace non-data with a zero-pad vector; and a circuit to detect a transmission error in data and zero-padded data portions of information, and combine the zero-pad vector with a remaining data portion to form the zero-padded data portion. The present invention enables a single error detection circuit to detect errors, thereby reducing chip area, increasing efficiency, and reducing power consumption.