Abstract: A packet parsing engine comprises a DMEM configured to store packet data; one or more registers configured to store parsing instructions or parse results; and one or more arithmetic logic units configured to parse the packet data based on the parsing instructions and to derive the parse results. The engine may be one engine of a plurality of engines configured to access a shared memory, and the engine may be configured to receive data from the shared memory or to send data to the shared memory. The DMEM may be divided into subsections, and at least one of the one or more registers may be divided into subsections, and the subsections may be configured such that while a DMEM subsection and its corresponding register subsection is parsing packet data for a first packet, one or more other subsections load packed data or unload parse results for a second packet.

Abstract: System and method of data routing according to a hierarchical scheduling process. Incoming data traffic is allocated to various queues of a buffer. A scheduling tree has a top level for queues, a bottom level for egress ports, and a plurality of intermediate levels corresponding to different granularities with respect to service categories. Each queue is assigned to a particular node in each intermediate level of the scheduling tree. The scheduling tree traverses through multiple scheduling stages from the bottom to the top level to select a winner node in each level based on a variety of fairness and differentiating variables. A queue associated with the winner nodes in various levels is selected for outgoing transmission at the selected egress port. Priority information is dynamically propagated from upper nodes to lower nodes such that a subsequent scheduling process uses the updated priority information.

Abstract: Aspects of the disclosure provide an operational transconductance amplifier (OTA) having an output stage. The output stage includes a first amplifier path configured to drive a first output current from a first power supply and a first resistor coupled between the first power supply and a source terminal of a first transistor in the first amplifier path. The first resistor is configured to improve a linearity of the OTA.

Abstract: An amplifier includes a first switch and a second switch each having a first terminal and a second terminal. The first terminals of the first and second switches respectively communicate with a first tank circuit and a second tank circuit. The second terminal of the second switch communicates with the second terminal of the first switch. A first capacitance having a first terminal connected directly to (i) the second terminal of the first switch and (ii) the second terminal of the second switch. A second terminal of the first capacitance is connected directly to a first input voltage of the amplifier. A first load is connected across (i) the first terminal of the first switch and (ii) the first terminal of the second switch. The amplifier generates a first output across the first load.

Abstract: Methods to identify a fluorescent lamp among multiple fluorescent lamps include: receiving input to a circuit including multiple fluorescent lamps operated by corresponding multiple control signals, each fluorescent lamp configured to output radio frequency (RF) signals in response to receiving a detection signal, the input to identify which first control signal is provided to a first fluorescent lamp; in response to receiving the input, providing a first discovery signal in place of each control signal provided to each fluorescent lamp, one fluorescent lamp at a time; determining that the first fluorescent lamp outputs RF signals; and identifying the control signal that was replaced with the detection signal that caused the first fluorescent lamp to output the RF signals.

Abstract: Method to identify a current drawn by a fluorescent lamp in a circuit. Methods include receiving a voltage supplied to a fluorescent lamp drawing a current in response to the voltage, digitally sampling the voltage at a sampling frequency and associating a first time stamp with a voltage value representing one of a maximum or minimum value in observed voltage, receiving the current after receiving the voltage, digitally sampling the current at the sampling frequency and associating multiple second time stamps with a corresponding multiple current values, identifying a second time stamp, a difference between the first time stamp and the second time stamp being within a threshold, and identifying a current value associated with the second time stamp as the current drawn by the fluorescent lamp.

Abstract: A system and method of extending a standard bridge to enable execution of logical bridging functionality are disclosed. In some implementations, a logical bridge may assign source logical port information to a data packet based on characteristics of the data packet, employ the source logical port information to learn the source address and to forward the data packet to a logical egress port, and map the logical egress port to a physical egress port at which the data packet is to be egressed. A tunnel interface may optionally be applied to a data packet upon egress.

Abstract: A resynchronization device for an Ethernet network device with a transmitter and a receiver includes a detector that detects faulty code groups received by the receiver. A counter counts the faulty code groups that are detected by the false carrier detector during a predetermined period. A resynchronization trigger asserts a resynchronization signal if the counter exceeds a predetermined threshold during the predetermined period. The faulty code groups include false carriers, which include non-idle code groups other than frame delimiters. Alternately, the faulty code groups include idle code groups that match idle code groups generated by the transmitter of the local network device.

Abstract: Methods and apparatus are provided for receiving a first signal and generating an output signal indicative of radio data system (“RDS”) information. A receiver circuit of the invention can include mixer circuitry, lowpass filter circuitry, downsampler circuitry, and decoder circuitry. Advantageously, the receiver circuit can operate entirely within the digital domain, promoting interoperability with digital frequency modulation (“FM”) demodulator circuitry.

Abstract: Among other disclosed subject matter, a magnetic disk controller can include an index detecting unit to detect an index of the magnetic disk, an error check code generating unit to, after the index detecting unit detects the index, generate a first error check code for first write data based on the first write data and a first physical address of a first sector subsequent to the detected index, and a writing control unit to cause the first error check code generated by the error check code generating unit, the first write data and the first physical address to be written into a second sector subsequent to the first sector.

Abstract: Among other disclosed subject matter, a magnetic disk controller includes an interface that receives and transmits data to be written into a magnetic disk. The magnetic disk controller includes a first buffer and a second buffer each of which temporarily stores data that is to be written into at least one sector of the magnetic disk. The magnetic disk controller includes an encoding unit that encodes the data stored in any of the first buffer and the second buffer into data representing a signal to be applied to the magnetic disk. A data width M between the encoding unit and the first and second buffers is at least equal to twice a data width N between the interface and the first and second buffers.

Abstract: A device previously configured as a registrar and that has established an independent ad-hoc network is automatically discovered by another device also previously configured as a registrar. To form an ad-hoc wireless network between these two devices, each device periodically enters a scanning mode to scan for and intercept beacons transmitted by the other device. Upon such interception, one of the devices becomes an enrollee in accordance with a predefined condition and in response to a user selected option. Subsequently, the enrollee modifies its beacons to include an attribute, such as the MAC address, associated with the other device. After intercepting the modified beacon, the remaining registrar prompts it user to decide whether to allow the enrollee to join the registrar's network. If the user responds affirmatively, a handshake is performed between the two devices and a subsequent attempt is made by the enrollee to join the registrar's network.

Abstract: A protocol governing the operation of an ad-hoc WLAN enables each device in the WLAN to be configured as a registrar and/or an enrollee. Accordingly, each device is configurable to support both the registrar as well as enrollee modes of operations. In response to a time-driven user action, the device may be configured to enter into a registrar mode or an enrollee mode. While in the registrar mode, the device enters into an aggressive beaconing phase by setting its beacon contention window to a relatively very small value. The aggressive beaconing increases the probability of the discovery of the registrar by the enrollees. Optionally the device may prompt the user to select between a registrar and an enrollee mode of operation by displaying the option on an LCD panel.

Abstract: A wire connection structure for an integrated circuit (IC) die includes a semiconductor wafer with an active device and/or a passive device. One or more dielectric layers are arranged adjacent to the active and/or passive device. One or more metal interconnect layers are arranged adjacent to the active and/or passive device. A contact pad is arranged in an outermost metal interconnect layer. A passivation layer is arranged over the outermost metal interconnect layer and includes at least one passivation opening that exposes the contact pad. A bond pad is arranged over the passivation layer and the active and/or passive device and is connected to the contact pad through the passivation opening. Formation of the bond pad does not damage the active and/or passive device.

Abstract: A programmable gain voltage buffer circuit with a programmable gain may include transistors in parallel with resistors. The transistors may be used as variable resistors, with the resistors predominating the equivalent resistances at output points in different branches of the buffer circuit. The transistors may have resistances corresponding to programmable gain steps in the circuit.

Abstract: Circuits, methods, and apparatus that provide low-noise, high-stability crystal oscillators having controlled-amplitude differential output signals and DC level control. A crystal oscillator circuit has two feedback loops, one for setting the DC level of its signals, the other for adjusting the amplitude of those signals. The DC level feedback loop can set the DC component of the oscillator signals to a voltage midway between two supply voltages. The amplitude control loop sets the amplitude of the output of the crystal oscillator signal to be within a range. The amplitude can be set to provide a maximum swing without clipping the supply voltages in order to provide high-stability and minimal jitter. The amplitude control circuit can also be digital for improved noise performance. The time constants of these two loops can be separated such that instabilities are avoided.

Abstract: Circuits, methods, apparatus, and code that provide low-noise and high-resolution electronic circuit tuning. An exemplary embodiment of the present invention adjusts a capacitance value by pulse-width modulating a control voltage for a switch in series with a capacitor. The pulse-width-modulated control signal can be adjusted using entry values found in a lookup table, by using analog or digital control signals, or by using other appropriate methods. The capacitance value tunes a frequency response or characteristic of an electronic circuit. The response can be made to be insensitive to conditions such as temperature, power supply voltage, or processing.

Abstract: A wire connection structure for an integrated circuit (IC) die includes a semiconductor wafer with an active device and/or a passive device. One or more dielectric layers are arranged adjacent to the active and/or passive device. One or more metal interconnect layers are arranged adjacent to the active and/or passive device. A contact pad is arranged in an outermost metal interconnect layer. A passivation layer is arranged over the outermost metal interconnect layer and includes at least one passivation opening that exposes the contact pad. A bond pad is arranged over the passivation layer and the active and/or passive device and is connected to the contact pad through the passivation opening. Formation of the bond pad does not damage the active and/or passive device.

Abstract: A monolithic CMOS phase-lock loop (PLL) circuit provides a high frequency of operation suitable for RF applications. The PLL produces an output clock with high spectral purity and very low jitter. The output clock has a low static phase error relative to a reference input, making the PLL useful for clock synchronizing applications, such as clock recovery elements in transmission/recording channels. The PLL provides in-phase and quadrature signals from a voltage controlled oscillator (VCO) which has two differential transconductors. The second differential transconductor has a positive input coupled to a positive output of the first differential transconductor, a negative input coupled to a negative output of the first differential transconductor, a positive output coupled to a negative input of the first differential transconductor, and a negative output coupled to a positive input of the first differential transconductor. Each differential transconductor has a negative output impedance.