Abstract: Some of the embodiments of the present disclosure provide an apparatus comprising a command cancellation channel (CCC) including a plurality of stages, the CCC configured to receive a first memory address of a sequence of memory addresses and a corresponding first modification command, determine that at least a first stage of the plurality of stages includes the first memory address and a corresponding second modification command, and erase the first memory address or cancel the second modification command while shifting the first memory address and the second modification command from the first stage to a second stage. Other embodiments are also described and claimed.

Abstract: Method and apparatus for modifying standard VLAN tags to perform network packet switching. The method includes receiving a data packet at a port of a network switch and determining whether the data packet has a virtual local area network (VLAN) tagged frame. If the received data packet has a VLAN tagged frame, then the method further includes modifying and encoding fixed portions of the VLAN tag frame with switching information. The switching information includes information for central management of data packet flow through the network switch.

Abstract: A hash function is applied to a set of data to generate a hash. A first subset of the hash is used to lookup an entry in a lookup table for a forwarding database. A second subset of the hash is used to identify, within the entry, data comprising an offset. The offset is applied to a location identified in the forwarding database by the first subset of the hash to determine an entry in the forwarding database. Optionally, the lookup mechanism is used in conjunction with one or more other forwarding databases. A method of updating the forwarding database within the double hash lookup framework is also described.

Abstract: A built-in-self-test (BIST) system for testing a memory that includes a scheduler module that generates a first test algorithm based on a set of operational codes. Each operational code defines a test operation to be performed by the first test algorithm on the memory. The BIST system also includes an execution module that applies the first test algorithm to the memory.

Abstract: Testing devices at various locations on a die may be used to determine one or more properties of the locations. For example, a testing device including an oscillator such as a ring oscillator at a location may be used to determine a silicon quality, temperature, and/or voltage at the location.

Abstract: Methods, circuits, architectures, and systems for error detection in transmitted data. The method generally includes the steps of (i) partitioning the unit of digital data into one or more full data lines and a remainder, wherein each of the full data lines comprises a predetermined number of data blocks, each of the data blocks has a first fixed length, the predetermined number is an integer of at least 2, and the remainder has a length less than the predetermined number times the first fixed length; (ii) if the remainder contains at least one data bit, adding to the remainder a padding vector having a length sufficient to generate a padded data line having the predetermined number of data blocks; and (iii) performing error checking calculations on the full data lines and the padded data line. The present invention reduces the chip area and power consumption, while improving system performance.

Abstract: Methods, circuits, architectures, software and systems for error detection in transmitted data. The method generally includes receiving data and non-data, the data including fixed length data portions, removing non-data; and if the data includes a remainder, adding a zero-pad vector to generate a zero-padded data portion, then checking the data and zero-padded data portions for a transmission error. The circuit generally includes a circuit to detect non-data; a circuit configured to replace non-data with a zero-pad vector; and a circuit to detect a transmission error in data and zero-padded data portions of information, and combine the zero-pad vector with a remaining data portion to form the zero-padded data portion. The present invention enables a single error detection circuit to detect errors, thereby reducing chip area, increasing efficiency, and reducing power consumption.

Abstract: Systems and techniques for producing a signal with a known phase relationship to a source clock at an output of an indeterminate circuit element such as a clock divider. The systems and techniques may be used to allow circuit test data to be accurately compared with simulation data.

Abstract: A circuit and related method of monitoring performance of an integrated circuit is provided comprising: using a variable oscillator that has an oscillation time period that varies within an expected range with variations in one or more of process, voltage or temperature to provide a signal that causes a count of a first counter to change at rate proportional to an oscillation frequency of the variable oscillator; using a clock source that has a frequency that substantially does not vary with variations in one or more of process, time or voltage to cause a count of a second counter to change at rate proportional to an oscillation frequency of the clock source; setting the second counter to start a count from a start; determining when the first counter has counted a reference count; and providing as a circuit speed, a value indicative of a count value produced by the second counter at about the moment when first counter finishes counting the count interval.

Abstract: A circuit generates a qualified data read strobe signal from a start burst signal and a bidirectional data strobe signal in a DDR memory control module. The circuit includes a delay module that receives the start burst signal and that generates a delayed start burst signal. An enable signal generator receives the delayed start burst signal and generates an enable signal. A first circuit generates the qualified data read strobe signal based on the enable signal and the bidirectional data strobe signal.

Abstract: A method and apparatus for managing packet memory is provided. The apparatus includes an empty list, a storage buffer and apparatus for updating the storage buffer and empty list. The empty list includes a multiplicity of single bit buffers. The storage buffer includes a multiplicity of contiguous buffers, wherein each single bit buffer is associated with one of the contiguous buffers. The state of the bit of a single bit buffer indicates the empty or full state of the associated contiguous buffer and the address of a contiguous buffer is a simple function of the address or number of its associated single bit buffer. The updating apparatus stores data in and removes data from the contiguous buffers and correspondingly updates the states of the associated single bits buffers.

Abstract: The present disclosure includes systems and techniques relating to FIFO queue memory. In general, in one implementation, a queue memory receives and stores information and supports first-in-first-out read and out-of-order read operations with information shifting within the memory relative to a read operation. The queue memory can include a write pointer that increments upon a write operation and decrements upon the read operation, a read pointer that identifies an oldest read entry of the queue memory when the read operation is a first-in-first-out read and that identifies a selected entry of the queue memory when the read operation is an out-of-order read, and a multiplexer operative to select entries of the queue memory responsive to the read pointer.

Abstract: A digitally controlled oscillator circuit is provided that comprises a ring oscillator including multiple inverters; multiple digitally controlled capacitors (DCCs), each coupled to apply a digitally controllable amount of capacitance to an output of a different one of the inverters; and control circuitry operable to change an amount of capacitance applied to each inverter during operation of the ring oscillator and to cause the multiple DCCs to apply substantially the same amounts of capacitance to each of the inverter throughout operation of the ring oscillator.

Abstract: Resources allocated to a group of ports include a plurality of storage regions. Each storage region includes a committed area and a shared area. A destination storage region is identified for a packet. A packet queuing engine stores the packet in the committed area of the determined destination storage region if it has a first drop precedence value, and if available storage space in the committed area exceeds a first threshold. The packet queuing engine stores the packet in the shared area of the determined destination storage region if the packet is not stored in the committed area, and if available storage space exceeds a second threshold defined by the packet's drop precedence value. If the packet is not stored either in the committed or shared area, it may be dropped.

Abstract: An inverted-phase detector is implemented in a system including a first clock circuit that provides a first clock signal and a delayed clock circuit that outputs an delayed clock signal. A reference circuit outputs a reference signal. A feedback circuit generates a feedback signal that is one of greater than and less than the reference signal when the first clock signal changes state before the second clock signal, and that is the other of greater than and less than the reference signal when the first clock signal changes state after the second clock signal.

Abstract: An embodiment of the present invention offloads the generation and monitoring of test packets from a Central processing Unit (CPU) to a dedicated network integrated circuit, such as a router, bridge or switch chip associated with the CPU. The CPU may download test routines and test data to the network IC, which then generates the test packets, identifies and handles received test packets, collects test statistics, and performs other test functions all without loading the CPU. The CPU may be notified when certain events occur, such as when throughput or jitter thresholds for the network are exceeded.

Abstract: A memory device and method for looking up data corresponding to an input address includes a memory lookup module, memory that communicates with the memory lookup module, and content addressable memory (CAM) that communicates with said memory lookup module.

Abstract: A method and computer program for verifying a design of a circuit comprises providing a model of the design; providing a first property for the design, wherein the first property describes a first behavior; checking the model using the first property and an environment of the design starting at a reset state until an example of the first behavior occurs; providing a second property for the design, wherein the second property describes a second behavior; and checking the model using the second property and an environment of the design starting at a state when the example of the first behavior occurs.

Abstract: A digital feedback loop circuit achieves a resolution as good as the intrinsic resolution of the delay element of the circuit, notwithstanding the presence of a feedback counter/divider of integer value N that might otherwise be expected to multiply the minimum resolution by N. Output altering circuitry is used to alter the error feedback signal for M out of every N feedback cycles in such a way that the overall delay over N cycles can be controlled to within the resolution of the delay element. In one embodiment, the output altering circuitry includes a second counter whose maximum value is controllable and that outputs a signal whose value changes after its current maximum value has been reached. In another embodiment, the output altering circuitry includes a lookup table preloaded with sequences of output signals, with the sequence selected by a controller.

Abstract: A method and computer program for verifying a design of a circuit comprises selecting a portion of a model of the design having a plurality of inputs and outputs; providing a property for the design that defines a predetermined behavior of one or more of the outputs; determining whether a stimulus exists that, when applied to the inputs of the portion, can produce a behavior other than the predetermined behavior at the outputs of the portion; when the stimulus exists, determining whether the model of the design of the circuit can produce the stimulus at the inputs of the portion of the model of the circuit; and when the stimulus cannot be produced by the model of the design of the circuit at the inputs of the portion of the model of the circuit, preserving a description of the stimulus for analysis.