Abstract: In a direct conversion receiver with zero-frequency intermediate frequency (IF) signal, the DC offset and 1/f noise of the IF signal is compensated by means of double-sampling. The first period of the doubling-sampling is a calibration phase, which stores the DC offset and the 1/f noise. The second period is a signal flow phase during which the stored DC offset and 1/f noise is connected in opposition with the IF signal to cancel the DC offset and 1/f noise.

Abstract: A MOSFET can operate as a resistor by operating in the linear or ohmic region of the drain V-I characteristics. This region can be obtained by floating the gate of the MOSFET, when the dc current and the voltage drop are given. Multiple resistors can be duplicated (or mirrored) by sharing the same source and floating gate. The floating gate voltage can be simulated using a closed loop equivalent circuit. Alternatively, the gate voltage can also be derived from the given drain-to-source voltage and the given current in a feedback loop. With this adaptive MOSFET resistor, the minimum supply voltage can be as low as the sum of the BJT threshold and the complementary BJT saturation voltage, e.g. VCC?VBE+Vsat (e.g. 0.8+0.15<1.0V). The threshold voltage Vt should be less than VBE.

Abstract: A BJT operating as a mixer has its collector biased at the knee of the IC vs VCE characteristic. A local oscillator voltage is applied to the base and an RF signal voltage is applied to the collector through a singled-ended emitter follower. The nonlinear curvature at the knee produces a beat frequency current. The base of the emitter follower can be fed from a current mirror or through an ohmic resistor. This mixer requires less supply voltage, and results in more conversion gain and less feed-through of the RF input signal than the Gilbert multiplier. Alternatively, the RF voltage can be applied to the gate and the local oscillator voltage can be applied to the drain. Sometimes, it is more desirable to invert the collector and the emitter, or to connect a normal transistor and an inverted transistor in parallel to optimize conversion gain.