Abstract: A two's complement multiplier is combined with additional circuit elements and implemented in an integrated circuit to provide a multiplier of selectively operating in two's complement or unsigned magnitude format. To achieve an unsigned magnitude product, the additional circuitry modifies or leaves unchanged the high-order half of the two's complement product as needed. Modification occurs when the most-significant bit of either or both multiplicand signals is a "1". When a multiplicand signal has a most-significant bit of "1", the non-most significant bits of the other multiplicand signal are added to the two's complement product to derive the unsigned magnitude product. Such an implementation results in insignificant speed loss and comparatively minor increase in the required silicon area.

Abstract: Method and apparatus process a composite video signal, converted it to component video signals which are processed digitally to produce reprogrammable digital RGB graphics signals. Specifically, a composite video signal is first digitized and then processed to convert digitized YUV component video signals into digitized RGB signals by means of a RAM-based table lookup technique optimized to the resolution of each of the component signals so as to minimize memory requirements and computation overhead. In a specific embodiment, a Y or luminance signal having a resolution of 6 bits is employed in connection with a V component signal having a resolution of 5 bits and a U component signal having a resolution of 3 bits without noticeable degradation of RGB color quality.