Abstract: A method and an apparatus for compensating for aging and temperature of the crystal in a crystal oscillator. An RF signal which is transmitted by a mobile telephone switching office (MTSO) (108) and received by the antenna (118). The signal transmitted by the MTSO (108) serves as an external reference. A crystal-controlled main oscillator/time base generator (134) provides a local reference frequency to the converters (120) and provides a time base signal to a counter (136). A controller (112) reads an aging correction value from a memory and provides a frequency control signal to the main oscillator (134). The converters (120) convert the received RF signal to an IF frequency. A limiter (122) provides a limited IF signal to the counter (136). Counter (136) counts the number of cycles of the limited IF signal that appear in a cycle of the time base signal. A controller (112) compares this measured count to a reference count and the count error is determined.

Abstract: A circuit for automatically limiting fluctuations in the output power level of a transmitter by providing a feedback control signal which is based on the output power level. An RF signal (100) is input to a terminal of the RF detector (200). When the RF signal (100) is more negative than a bias voltage (209), a capacitor (208) begins charging. When the RF signal (100) becomes more positive than the bias voltage (209), the voltage in the charged capacitor (208) is added to the RF signal (100) and then averaged by the capacitors (214 and 206) to form voltage VE. Voltage VE in conjunction with the current setting circuitry (230) establishes a tail current (235) which is comprised of transistor (216) current (225) and the current from the RF detector (200). The tail current (235) tends to remain constant whereas the transistor current (225) is responsive to power changes in the RF signal (100) and represents the difference between the output power level of the RF power amplifier and the specified reference (110).

Abstract: A nozzle for a vacuum mounting head of a component placement machine. The nozzle includes a positioning block defining a plurality of spaced apart pads on top of the block with each of the pads having a pad hole in the top of the pad. The positioning block also defines an opening in the bottom of the block for mounting the nozzle on the vacuum mounting head. The positioning block further defines an interior air passage connecting each of the pad holes with the opening in the bottom of the block for the application of a vacuum force by the nozzle.

Abstract: A tunable filter (25) is described for use in loop control circuits. The filter (25) has a time constant which is determined by a resistor (40) and a capacitor. The capacitor is simulated by the series combination of an impedance converter (41) and a variable resistor, such as a field effect transistor (42). The resistance of the transistor (42) is determined by a control signal present on a control line (32) and the impedance converter (41) converts the resistance into an equivalent capacitive reactance. Therefore, the control signal on the control line (32) effectively controls the capacitance present at a node (43) and, in conjunction with the resistor (40), determines the time constant, and therefore the response time and bandwidth, of the filter (25). Multiple pole, lowpass, bandpass, highpass, and bandstop filters can be constructed. The impedance converter (41) uses a very small capacitor to simulate a large capacitance value at the node (43).

Abstract: A detector for determining the validity of a received code, such as a Digital Supervisory Audio Tone (DSAT) code. A received DSAT code is serially shifted into a shift register (10) which outputs the received DSAT code in parallel format to a set of 24 exclusive-OR gates (12). Another shift register (11) receives a valid code, such as a valid DSAT code. The register (11) outputs the valid DSAT code, and right circular shifted (rotated) versions of the valid DSAT code, to the gates (12). The comparison signal from the gates (12) is provided to another register (13) and a counter (16) which together count the number of mismatches between the received DSAT code and the reference DSAT codes. The output of the counter (16) is provided to a comparator (17) which compares the number of mismatches against the allowable number of mismatches. The output of the comparator (17) is a validity signal (7) which indicates whether the received DSAT code matches any of the reference DSAT codes.

Abstract: A dual mode quadrature detector (15) uses the same components for both narrow band and wide band operation and provides an output amplitude which is independent of the mode of operation selected. A multiplier (32) provides a demodulated output signal (16) which is responsive to the phase difference between a signal (14) at one input (32A) and a phase shifted version of the signal at the other input (32B). A capacitor (30) and a phase shifting circuit (31) provide the phase shifted version of the signal. The phase shifting circuit (31) is responsive to a mode control signal (24) for determining the phase shift which is provided. The phase shift at the maximum frequency deviation of the narrow band signal is the same as the phase shaft at the maximum deviation of the wide band signal so that the output amplitude from the detector (15) is the same for both narrow band and wide band operation. The phase shift provided is controlled by varying the quality factor (Q) of the phase shifting circuit (31).

Abstract: An automatic level control circuit for radio frequency power amplifiers which is immune to temperature and power supply induced variations. The level control circuit (42) employs a detector/comparator comprising a matched transistor pair (55) operating as a detecting differential amplifier to compare a reference signal (63) to the output power signal (83). A second amplifier (60) receives the differential output signals from the detecting amplifier and provides a power level control signal (97) to the power amplifier, thereby causing the power amplifier to produce the desired output power level.

Abstract: A two-stage direct conversion receiver. A first mixer (13) converts the incoming signal to an intermediate frequency (IF) signal. A second mixer (16) converts the IF signal to a baseband signal. A detector (17), receiver logic circuit (18), and alerting device circuit (19) act upon the baseband output signal. A two port oscillator (14) provides a fundamental frequency output (FO) and a tripled output frequency (3 FO). The tripled output frequency is again tripled (9 FO) by a frequency multiplier (15) and is provided as a mixing signal to the first mixer (13). The fundamental frequency output is provided to a phase locked loop (20, 21, 22). The output frequency (FV) of the phase locked loop is doubled (2 FV) by a frequency multiplier (23) and provided to a phase shift circuit (24). The output of the phase shift circuit (24) is provided as the second mixing signal to the second mixer (16).