Patents Assigned to Matsushita-Kotobuki Electronics Industries, Ltd.
  • Publication number: 20020148753
    Abstract: The present invention relates to a tray used for transporting a number of hard disk drive heads (HDD heads). The tray (10) according to the invention has small-projections provided on a part of the surface of the positioning part (12, 15) which contacts the HDD head (30) when the HDD heads (30) are set in the tray (10). An example of the small-projection (20) is a hemispherical projection (20) whose height is slightly larger than the thickness of the wiring (34) (e.g. about a few to several hundreds of micrometers). Another example of the small-projection is a ridge (21) of about one to several hundreds of micrometers in diameter and about a few millimeters in length. By virtue of such a design, the friction between the wire-applied surface of the HDD head (30) and the positioning part (12, 15) of the tray (10) is substantially reduced because they contact with each other only at the top of the small-projection (20, 21).
    Type: Application
    Filed: June 6, 2002
    Publication date: October 17, 2002
    Applicant: EGAMI CHEMICAL CO., LTD., NISSHO CORPORATION and MATSUSHITA-KOTOBUKI ELECTRONICS INDUSTRIES, LTD.
    Inventor: Nobuo Egami
  • Patent number: 6416936
    Abstract: A top surface imaging technique for top pole tip width control in a magnetoresistive (“MR”) or giant magnetoresistive (“GMR”) read/write head is disclosed in which a multi-layer structure is employed to define the thick photoresist during processing resulting in much improved dimensional control. To this end, a relatively thin upper photoresist layer is patterned with much improved resolution, an intermediate metal or ceramic layer is then defined utilizing the upper photoresist layer as a reactive ion etching (“RIE”) mask, with the intermediate layer then being used as an etching mask to define the bottom-most thick photoresist layer in a second RIE process. As a consequence, a much improved sub-micron pole tip width along with a high aspect ratio and vertical profile is provided together with much improved critical dimension control.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: July 9, 2002
    Assignee: Matsushita-Kotobuki Electronics, Industries, Ltd.
    Inventors: Michael J. Jennison, Wei Pan
  • Patent number: 6356410
    Abstract: A head structure for writing data on a magnetic media including a first pole having an upper surface and a write gap covering a portion of the upper surface. An upper pole tip formed on the write gap having a first width. A second pole having a second width greater than the first width and coupling to an upper surface of the upper pole tip. A conductive coil magnetically coupled to the first pole and the second pole to induce magnetic flux within the first and second pole in response to a current flowing in the coil.
    Type: Grant
    Filed: June 12, 2000
    Date of Patent: March 12, 2002
    Assignee: Matsushita-Kotobuki Electronics Industries, Ltd.
    Inventors: Robert Chesnutt, Charles Partee, Pierre Asselin, John Biesecker, John Fleming, Mike Jennison, Francis Campos, Steve Sanders
  • Patent number: 6156487
    Abstract: A top surface imaging technique for top pole tip width control in a magnetoresistive ("MR") or giant magnetoresistive ("GMR") read/write head is disclosed in which a multi-layer structure is employed to define the thick photoresist during processing resulting in much improved dimensional control. To this end, a relatively thin upper photoresist layer is patterned with much improved resolution, an intermediate metal or ceramic layer is then defined utilizing the upper photoresist layer as a reactive ion etching ("RIE") mask, with the intermediate layer then being used as an etching mask to define the bottom-most thick photoresist layer in a second RIE process. As a consequence, a much improved sub-micron pole tip width along with a high aspect ratio and vertical profile is provided together with much improved critical dimension control.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: December 5, 2000
    Assignee: Matsushita-Kotobuki Electronics Industries, Ltd.
    Inventors: Michael J. Jennison, Wei Pan
  • Patent number: 6099699
    Abstract: A process for providing a thin encapsulation layer for thin film heads includes controlling the bias voltage of the substrate and head during the encapsulation layer deposition process. The bias voltage is first maintained at approximately 60 volts while the standard encapsulation overcoat portion of the layer is deposited. This may take approximately one hour. Over the next thirty minutes, the bias voltage is ramped from approximately 60 volts to approximately 200 volts in a gradual, linear manner to reduce the stress on the wafer and heads. The bias voltage is then maintained at approximately 200 volts for the next three hours while the remainder of the encapsulation layer is deposited. Because of the higher bias voltage, the layer is deposited in a substantially planar manner so that there is no need for a lapping back process. Stress to the head is minimized by ramping the bias voltage. In addition, relatively short studs can be used for routing signals to and from the read/write elements of the head.
    Type: Grant
    Filed: April 22, 1998
    Date of Patent: August 8, 2000
    Assignee: Matsushita-Kotobuki Electronics Industries, Ltd.
    Inventors: Wei Pan, Ann Kang, Jerome Marcelino
  • Patent number: 5563868
    Abstract: Coherent light passing through slits produces an optical interference pattern having a fringe spacing related to the spacing of the servo tracks on a magnetic disk. The convolution of the interference pattern with the servo tracks generates a servo error signal.
    Type: Grant
    Filed: February 14, 1995
    Date of Patent: October 8, 1996
    Assignee: Matsushita-Kotobuki Electronics Industries, Ltd.
    Inventors: Stephen W. Farnsworth, Scott D. Wilson
  • Patent number: D456832
    Type: Grant
    Filed: April 25, 2000
    Date of Patent: May 7, 2002
    Assignee: Matsushita Kotobuki Electronics Industries, Ltd.
    Inventors: Andrew Serbinski, Mirzat Koc, Masakazu Mori
  • Patent number: D459320
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: June 25, 2002
    Assignee: Matsushita-Kotobuki Electronics Industries, Ltd.
    Inventors: Andrew Serbinski, Mirzat Koc
  • Patent number: D462335
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: September 3, 2002
    Assignee: Matsushita-Kotobuki Electronics Industries, Ltd.
    Inventors: Andrew Serbinski, Mirzat Koc
  • Patent number: D464069
    Type: Grant
    Filed: May 29, 2001
    Date of Patent: October 8, 2002
    Assignee: Matsushita-Kotobuki Electronics Industries, Ltd.
    Inventors: Andrew Serbinski, Mirzat Koc, Masakazu Mori