Abstract: In-flight operations in an inbound data path from a source memory to a convolution hardware circuit increase computational throughput when performing convolution calculations, such as pooling and element-wise operations. Various operations may be performed in-line within an outbound data path to a target memory. Advantageously, this drastically reduces extraneous memory access and associated read-write operations, thereby, significantly reducing overall power consumption in a computing system.

Abstract: Presented are systems and methods for automatically creating and labeling training data for training-based radio, comprising receiving, at a receiver, a frame that comprises a modulated radio frequency (RF) signal comprising a set of waveforms that correspond to payload data. The payload data comprises a sequence of random bits. In embodiments, until a stopping condition is met one or more steps are performed, comprising detecting the frame; demodulating the modulated RF signal to reconstruct the sequence of random bits; using the reconstructed sequence to determine whether the payload data has been correctly received; in response to determining that the payload data has not been correctly received, discarding it and, otherwise, accepting the sequence of random bits as a training label; associating the training label with the modulated RF signal to generate labeled training data; and appending the labeled training data to a labeled training data set.

Abstract: Systems and methods allow existing hardware, such as commonly available hardware accelerators to process fully connected network (FCN) layers in an energy-efficient manner and without having to implement additional expensive hardware. Various embodiments, accomplish this by using a “flattening” method that converts a channel associated with a number of pixels into a number of channels that equals the number pixels.

Abstract: Storage-efficient, low-cost systems and methods provide embedded systems with the ability to dynamically perform on-device learning to modify or customize a trained model to improve computing and detection accuracy in small-scale devices. In certain embodiments, this is accomplished by repurposing storage elements from inference to training and performing partial back-propagation in embedded devices in the final layers of an existing network. In various embodiments replacing weights in final layers, while using hardware components to iteratively performing forward-propagation calculation, advantageously, reduces the need to store intermediate results, thus, allowing for on-device training without significantly increasing hardware requirements or requiring excessive computational memory resources when compared to conventional machine learning methods.

Abstract: A first module is configured to, based on an input sample, determine a first duty cycle. A second module is configured to, based on a battery voltage and the first duty cycle, determine a second duty cycle. A third module is configured to: set a scalar value based on at least one of a battery current, an amplitude of the input sample, the second duty cycle, and an output voltage; and generate a start signal at a rate equal to a predetermined rate multiplied by the scalar value. A fourth module is configured to set a third duty cycle based on the second duty cycle and the scalar value. A fifth module is configured to generate a PWM output based on the start signal and the third duty cycle. A sixth module is configured to apply power to gates of FETs of a voltage converter based on the PWM output.

Abstract: A novel energy-efficient multiplication circuit using analog multipliers and adders reduces the distance data has to move and the number of times the data has to be moved when performing matrix multiplications in the analog domain. The multiplication circuit is tailored to bitwise multiply the innermost product of a rearranged matrix formula to output the generate a matrix multiplication result in form of a current that is then digitized for further processing.

Abstract: Systems and methods reduce power consumption in embedded machine learning hardware accelerators and enable cost-effective embedded at-the-edge machine-learning and related applications. In various embodiments this may be accomplished by using hardware accelerators that comprise a programmable pre-processing circuit that operates in the same clock domain as the accelerator. In some embodiments, tightly coupled data loading first-in-first-out registers (FIFOs) eliminate clock synchronization issues and reduce unnecessary address writes. In other embodiments, a data transformation may gather source data bits in a manner that allows loading full words of native bus width to reduce the number of writes and, thus, overall power consumption.

Abstract: Described herein are system and method embodiments of acoustic augmentation of haptic vibration with correlated sounds. Embodiments of a haptic driven signal crossing both vibration band and acoustic band are disclosed. The driven signal at the acoustic band enables a haptic in an electronic device to provide an audio augmentation for haptic vibration independent from a loudspeaker of the electronic device. Upon a touch on a touch surface is detected, a vibration request is generated based on the touch and user preferences. A pattern generator is used to generate a vibration signal based on the vibration request to drive a haptic vibrator for desired vibration and acoustic sound patterns.

Abstract: LMS adaption systems and methods disclosed herein adaptively switch between modes of operation that selectively avoid using the imaginary part of an error signal, in effect, allowing for an LMS adaption that switches between utilizing only the real part of the error signal and utilizing the full complex error signal. Various embodiments take advantage of this added flexibility by implementing a dynamic power saving scheme that, for example, during times when high tracking performance (e.g., high accuracy or high SNR) is not needed, saves power by not energizing a number of multiplier and adder circuits that are expensive in terms of power consumption, thereby, trading power savings for a possible temporary reduction in tracking performance. In embodiments, power savings are accomplished by adaptive power-gating systems and methods that in parts of an analog LMS adaption circuit turn on and off current sources in analog multiplier circuits on demand.

Abstract: Described are context-aware low-power systems and methods that reduce power consumption in compute circuits such as commonly available machine learning hardware accelerators that carry out a large number of arithmetic operations when performing convolution operations and related computations. Various embodiments exploit the fact that power demand for a series of computation steps and many other functions a hardware accelerator performs is highly deterministic, thus, allowing for energy needs to be anticipated or even calculated to a certain degree. Accordingly, power supply output may be optimized according to actual energy needs of compute circuits. In certain embodiments this is accomplished by proactively and dynamically adjusting power-related parameters according to high-power and low-power operations to benefit a machine learning circuit and to avoid wasting valuable power resources, especially in embedded computing systems.

Abstract: Described herein are systems and methods that prevent against fault injection attacks. In various embodiments this is accomplished by taking advantage of the fact that an attacker cannot utilize a result that has been faulted to recover a secret. By using infective computation, an error is propagated in a loop such that the faulted value will provide to the attacker no useful information or information from which useful information may be extracted. Faults from a fault attack will be so large that a relatively large number of bits will change. As a result, practically no secret information can be extracted by restoring bits.

Abstract: A method and a circuit arrangement for damping stepper motor resonances during operation of a stepper motor, in particular in the medium and high speed range, is described, wherein the coils of the stepper motor are each connected into a bridge circuit comprising semiconductor switches, in order to impress into the coils a predetermined target coil current. The resonance damping is achieved by activating a passive FD-phase in the zero crossing of the target coil current, during which all semiconductor switches are opened or switched blocking, in order to thereby feed a coil current flowing in the related motor coil back into the supply voltage source either via inverse or body diodes and/or via diodes connected in parallel to the semiconductor switches in the reverse direction between the positive supply voltage and ground potential.

Abstract: A system for monitoring and controlling an IC testing machine includes a vibration sensor, a sensor interface, and a processor coupled to the sensor interface. The vibration sensor is in mechanical communication with an IC testing machine to develop an electrical vibration signal representing mechanical vibrations generated by the operation of the IC testing machine. The sensor interface processes the vibration signal to develop vibration data that can be processed by the processor to determine whether the vibration data is indicative of an operational anomaly and, if so, to generate a machine control signal to correct an operation of the IC testing machine. Multiple vibration sensors can be used to increase the amount of vibration data available for analysis.

Abstract: An apparatus including a handshake window enabler having a pair of differential inputs and a window enablement output, a common mode detector coupled to a power input and a ground input and having a handshake inhibit output, and a handshake disabler coupled to the handshake window enabler, the common mode detector, and the pair of differential inputs. If a common mode voltage that out of range (“too high”) is detected, high speed handshake protocols are such that the bus operates a lower data rate.

Abstract: A current sensing line fault detector includes a unity gain buffer coupling a reference voltage to an IC pin, a current controlled current source coupled to the buffer, a current mode A/D converter developing a digital signal representative of the IC pin current, and logic for determining the state of a transmission line coupled to the IC pin. An alternative current sensing line fault detector includes an OPAMP having a first input coupled to an input node and to a reference current source and having a second input coupled to a reference voltage source. A voltage controlled current source (VCCS) is coupled between the first input of the OPAMP and ground and is controlled by an output of the OPAMP. An A/D converter is coupled to the output of the OPAMP to develop a digital output signal representative of the current flowing through the current sensor.

Abstract: Circuitry, systems, and methods for fault detection and reporting comprise a fault detection circuit configured to detect one or more fault conditions that cause a state change in a fault pin voltage representative of a transceiver failure. Once the state of the fault pin voltage changes, a transceiver input generates a fault detection code. In embodiments, in response to the transceiver input receiving a first signal, the fault detection code is shifted to a transceiver output that may communicate the fault detection code to a controller. Once the transceiver input receives a second signal, the fault pin voltage may be reset to clear the fault detection code before resuming operations, including detecting additional fault conditions as they arise.

Abstract: Described herein are systems and methods for operating DC-DC regulators such as LED drivers. Various embodiments herein allow a DC-DC regulator to switch between buck mode and buck-boost mode without suffering effects otherwise resulting from transient currents when switching between modes. In certain embodiments, this is accomplished by operating the DC-DC regulator in a buck-boost mode to charge a boost capacitor with a substantially constant inductor current. The inductor current is also used to control a set of switches to operate the DC-DC regulator in a buck mode to drive a load by using the capacitor as a power source.

Abstract: Described herein are systems and methods that perform coarse chromatic dispersion (CD) compensation by applying precomputed coarse front-end equalizer (FEE) tap weights to a receiver based on an assumed propagation distance. After a waiting period, the FEE tap weights are applied, and it is determined whether the FEE tap weights cause a decision-directed tracking of channel rotations to satisfy a stability metric. In response to the stability metric not being satisfied, the assumed propagation distance is adjusted and used to obtain updated FEE tap weights. Conversely, if the stability metric is satisfied, a fine CD compensation is performed that comprises maintaining the updated FEE tap weights; performing an iterative least-mean-squared (LMS) error adaption to adjust Back-End Equalizer (BEE) tap weights and obtain updated BEE tap weights; and using the updated BEE tap weights to adjust the FEE tap weights to, ultimately, have the BEE output an equalized data bit stream.

Abstract: A solenoid system and method can include: providing an energizing voltage to a coil of a solenoid; providing an AC signal superimposed onto the energizing voltage; detecting current through the coil including an AC current amplitude induced by the AC signal and including a DC offset current amplitude; determining the AC current amplitude is a low AC current amplitude based on an armature within the solenoid being in a retracted position or determining the AC current amplitude is a high AC current amplitude based on the armature being in an extended position with the control logic, and where the AC current amplitude is determined utilizing the AC signal for synchronous demodulation; and determining a temperature fault based on the DC offset current amplitude falling below a DC offset current amplitude threshold.

Abstract: Described herein are systems and methods for reliably detecting of the presence or absence of accessories and other components connected to an external electrical device or connector. A low-cost detection circuit reliably distinguishes between a compromised connector and the presence of an actual device, thereby, preventing false detection scenarios. In various embodiments, the detection circuit accomplishes this by using a zero-crossing detector and/or a digital signal, which serves as a measure of impedance, to detect, within an identification period, the presence of the external device.