Abstract: A routing table circuit for a router has one or more input ports and output ports for message communication. In the routing table circuit, one or more routing table memories store a plurality of routing table arrays. The routing table arrays are arranged hierarchically in levels, and each routing table array is associated with a predetermined subset of prefixes. Each routing table array has entries. The entries include a block default route pointer field to store a block default route pointer, if any, and a routing field. The route engine may access any level of table array by using a next level route pointer stored in the routing field. Using the block default route and the routing field, the present invention further reduces the number of memory accesses and the update cost for route insertion and deletion by identifying and skipping elements that do not require route updating.

Abstract: A deterministic routing table includes a set of hash circuits and a CAM. The routing table searches for the longest matching destination address stored in any of the hash circuits and the CAM, if any, and outputs an output pointer associated with that destination address within a fixed predetermined time.

Abstract: A SONET bus has a set of SONET mappers that transmit and receive facility signals on facility lines. Each facility line operates at a predetermined speed. Each SONET mapper generates a SONET signal by mapping the facility signals received by the SONET mapper into a predefined format for transmission. The predefined format includes timeslots associated with each received facility signal. Each SONET mapper receives a SONET signal and maps the received SONET signal into the facility signals transmitted by the SONET mapper on the facility lines. Each SONET signal includes an associated set of the facility signals. At least one counter outputs a timeslot count signal for synchronizing the timeslots of the facility signals. A set of bidirectional drivers has a mapper side and a system side. Each bidirectional driver receives the timeslot count signal.