Abstract: Color-difference signals that become unnecessary after rotation are deleted from a second pixel while saving color-difference signals that become necessary after rotation in the second pixel, to thereby form image data conforming to YUV422 format. The image data is then rotated, and subsequently the color-difference signals saved in the second pixel are returned to the original first pixel, to thereby form image data conforming to YUV422 format.

Abstract: A pixel signal of Bayer pattern output from an imaging device is subjected to interpolation in a pixel interpolation circuit, and converted into a YCbCr signal in a color space conversion circuit. A chroma value calculation circuit calculates a chroma value based on the pixel signal output from the imaging device. A look-up table converts the chroma value into a suppression signal. More specifically, when the chroma value is lower than a threshold value, the look-up table outputs a value lower than 1 as the suppression signal. The suppression signal is corrected in another look-up table, and then, works on Cr and Cb signals in multipliers. A signal in a low-chroma region is thereby suppressed.

Abstract: The present invention provides a memory device of a type that outputs a ready signal to the outside, and that is capable of achieving an enhanced data transfer rate and a uniform latency time. A memory device according to the present invention includes a ready signal sending portion, and the ready signal sending portion monitors a memory portion to detect the memory portion becoming ready for reading or writing of specified data. The ready signal sending portion generates a first ready signal that changes from a busy state to a ready state after the detection and an enabling signal that changes from a disable state to an enable state on the basis of a preset ready generating timing value. When the first ready signal is in the ready state and the enabling signal is in the enable state, the ready signal sending portion sends to the outside a second ready signal that is in a ready state.

Abstract: Correlation values in the vertical direction, horizontal direction and two diagonal directions are obtained in a pixel signal of RGB Bayer pattern. The correlation values are calculated using G signals. Between a first pair of the vertical and horizontal directions and a second pair of the two diagonal directions, one pair having a greater correlation difference is selected. Then, a direction having a stronger correlation is selected in the selected pair having a greater correlation difference, and pixel interpolation is performed in the selected direction. Alternatively, pixel interpolation is performed following assignment of weights in two directions of the selected pair having a greater correlation difference in accordance with the proportion of their correlations.

Abstract: A first pixel group containing a pixel of interest, a second pixel group containing the first pixel group, and a third pixel group containing the second pixel group are defined. A first reference pixel value is calculated based on the first pixel group, and a second reference pixel value is calculated based on the third pixel group. The second pixel group is divided into two sub-groups with respect to the second reference pixel value. The sub-group containing the pixel of interest is selected as a target set. In the target set, a pixel with a pixel value close to the first reference pixel value is selected as a corrective pixel. The pixel value of the pixel of interest is replaced with the pixel value of the corrective pixel.

Abstract: The present invention provides a semiconductor storage device that requires no specialized circuit or the like for reading redundancy data from a redundancy region, and that is capable of freely changing the arrangement of the redundancy region in the memory array area. A semiconductor storage device of the present invention includes a memory array configured as shown below. The memory array includes a user region which is composed of given page units and where user data is stored, and a redundancy region which is composed of the same given page units and where redundancy data is stored. The area in the memory array can be used either as the user region or as the redundancy region.

Abstract: Color-difference signals that become unnecessary after rotation are deleted from a second pixel while saving color-difference signals that become necessary after rotation in the second pixel, to thereby form image data conforming to YUV422 format. The image data is then rotated, and subsequently the color-difference signals saved in the second pixel are returned to the original first pixel, to thereby form image data conforming to YUV422 format.

Abstract: A refresh controller transmits two refresh request signals of a first request signal which indicates a time at which a refresh operation of a DRAM may be performed and a second request signal which indicates a time at which a refresh operation of the DRAM must be performed, to an arbitrator. On the other hand, also transfer request signals each of which requests a data transfer are transmitted from plural data transfer parts, respectively, to the arbitrator. If no transfer request signal is input when a first request signal is input to the arbitrator, a refresh operation of the DRAM is performed. As a result, a refresh operation is performed when the crowding level of a bus is relatively low. This improves an efficiency in a data transfer.

Abstract: In an OTP memory, initially, a file A is recorded. When modification of the file A is needed, a modification file B is additionally written into the OTP memory. Storage information on the modification file B is also additionally written into a FAT area and a directory entry. When an application program issues a read request for the file A, a file system refers to the FAT area and the directory entry to recognize the existence of the modification file B and reads the file A and the modification file B out from a data area. Then, the file system modifies the file A on the basis of the modification file B and stores a modified file into a RAM. The application program accesses the file which is stored in the RAM.

Abstract: While a semiconductor memory operates in a first operation mode with high security, an encrypted command is inputted and then decoded to acquire the first address information. After the semiconductor memory comes into a second operation mode where the level of security is lower than that of the first operation mode, a command is inputted. Then, the second address information is acquired from the command. A control circuit in the semiconductor memory generates an address of 10 bits by using the first address information as a high-order 4 bits and the second address information as a low-order 6 bits and outputs the address to a memory array. With this operation, it becomes possible to read/write data from/to the memory array.

Abstract: A bank controller, an information processing device, an imaging device, and a control method are provided which enable improved data communication processing between FIFO memories of processing blocks and a synchronous DRAM. An arbiter determines the order of priorities in data communication performed between FIFO memories and associated banks. A precharge period detecting block detects the states of precharge of the banks. A register stores data required to determine the order of priorities (data indicating whether the banks are in a precharge period, data indicating whether data communication request signals are presented). This enables the arbiter to exclude FIFO memories that are associated with banks that are not allowed to perform data communication. Efficient data communication is thus implemented between the FIFO memories and the synchronous DRAM.

Abstract: The least significant bits of respective count values of an H counter and a V counter are combined, to generate a timing signal defining a 2×2-size repeat block. A timing register including four registers each storing data which determines a color of each location within the repeat block is provided for each of input channels. A selector selects one of outputs of the timing registers based on the timing signal, and generates a signal designating a color of a pixel at a certain time for each of the input channels. A register storing black level correction data for each color is used in common by the input channels. For each of the input channels, an item of black level correction data at the certain time is selected based on the signal designating the color of the pixel at the certain time and input to a pre-processing circuit in each of the input channels.

Abstract: For an electronic apparatus in which data is transferred between a plurality of processing devices and a memory, a technique is provided which prevents the data transfer from being restricted and allows the processing devices to operate efficiently. The order of priorities of data transfer operations through channels is changed on the basis of a relation between thresholds and the amounts of data remaining respectively in FIFO buffers. This prevents the FIFO buffers from becoming empty of data, or from being filled up with data, which allows the devices to operate efficiently.

Abstract: The present invention provides a semiconductor storage device that requires no specialized circuit or the like for reading redundancy data from a redundancy region, and that is capable of freely changing the arrangement of the redundancy region in the memory array area. A semiconductor storage device of the present invention includes a memory array configured as shown below. The memory array includes a user region which is composed of given page units and where user data is stored, and a redundancy region which is composed of the same given page units and where redundancy data is stored. The area in the memory array can be used either as the user region or as the redundancy region.

Abstract: A memory cell array includes a memory cell transistor storing data of a value in accordance with a set threshold voltage. A writing control unit controls writing of data in the memory cell transistor. A memory cell driving unit writes data in the memory cell transistor under the control of the writing control unit. The writing control unit is capable of setting at least three types of threshold voltages having different values for the memory cell transistor by controlling the memory cell driving unit, and uses only a plurality types of threshold voltages having values not adjacent to each other of the at least three types of threshold voltages in writing data in the memory cell transistor.

Abstract: The present invention has an object to enrich expression of contents of an e-mail message. In a mobile phone (1), text data (TxD) is input, and a 3D authoring operation is carried out. The text data (TxD) and 3D authoring instruction data (DD) are transmitted from the mobile phone (1) to a server (3), and then, scenario data (SD) which is control information about 3D graphics is generated in the server (3). The text data (TxD) and scenario data (SD) are stored in the server (3) as 3D message information (MD). When access information to the 3D message information (MD) is notified from the mobile phone (1) to a mobile phone (2), the mobile phone (2) makes access to the server (3) to download the 3D message information (MD) and a necessary 3D font. 3D character mail is thereby reproduced in the mobile phone (2).

Abstract: A similar-image detecting part detects similar image regions similar to one another in a plurality of frame images captured by rolling shutter type exposure. A displacement-vector detecting part detects a displacement vector of each of the similar image regions with respect to a reference position in each of the plurality of frame images. An average calculating part calculates an average of displacement vectors in the plurality of frame images. A correcting part shifts a similar image region in one of the plurality of frame images such that the displacement vector of the similar image region becomes the average calculated by the average calculating part.

Abstract: Pixel signals are sequentially output from an image sensor in a reverse order to an order in which light sensing cells are arranged with respect to one of a horizontal direction and a vertical direction. In an image processor, first, a data reading part transfers the pixel signals in the same order as corresponding light sensing cells are arranged with respect to both of a horizontal direction and a vertical direction, and a signal sequence of the pixel signals is changed. Then, the pixel signals which are output group by group are sequentially selected by a selector in accordance with a sequence of groups. As a result, the pixel signals can be supplied from the selector in an order conforming a two-dimensional array of the light sensing cells, to thereby facilitate color interpolation which is to be later performed by a color interpolator.

Abstract: A file management information area of a memory includes a FAT and a replacement information table. In the FAT, chain information on a file is recorded and in the replacement information table, replacement information of a defective area is recorded. In order to read out the file, a file system reads out the FAT and the replacement information table to generate indexes of the file and stores the indexes to an index buffer. In a memory controller, an address part of a read command is sequentially replaced with indexes stored in the index buffer and page-replaced read commands are continuously transferred to the memory.

Abstract: In a memory, a file is stored at discontinuous page addresses. The information thereon is recorded in FAT of the memory. When an application program in a host system performs a read operation for the file, a FAT system refers to the FAT to read out page indexes of the file. Then, the page indexes are stored in a page index buffer included in a memory controller. When a DMAC outputs a read command, a page index transfer sequencer replaces an address part of this read command with the page indexes and outputs page-replaced read commands to the memory.