Abstract: The present invention discloses a DMOS transistor cell, supported on a substrate of a first conductivity type. The DMOS transistor cell includes a body region of a second conductivity type disposed in the substrate defining a central portion of the cell. This DMOS transistor cell further includes a trench gate filled with polysilicon therein surrounding the body region and defining a boundary of the cell. This DMOS transistor cell further includes a source of the first conductivity type defined by a narrow strip of source region disposed in the body region along an edge thereof adjacent to the trench gate.

Abstract: Improved power MOSFET structure, and fabrication process are disclosed in this invention to achieve cost savings by simplified device structure and fabrication processes, and also by reducing the required die size. Specifically, in a novel MOSFET device, insulation of mobile ions are achieved by extending the poly gate and metal contacts such that the passivation layer is no longer required and the fabrication process is simplified such that the MOSFET device can be manufactured at a lower price. Furthermore, in another MOSFET device, the gate runner is used to replace the field plate such that the requirement of a field plate as that in a conventional MOSFET device is also eliminated and, by reducing the die size, the cost of manufacture is further reduced.

Abstract: The present invention includes a substrate of a first conductivity type having a top surface including at least two intersecting trenches disposed therein with an insulating layer lining the trenches and a conductive material filling the trenches. The transistor also includes a source region of the first conductivity type extending from the top surface of the substrate adjacent to the trenches toward the substrate. The transistor further has a body region of a second conductivity type of opposite polarity from the first conductivity type, the body region extends from the top surface adjacent from the trenches to the substrate and surrounding the source region.

Abstract: The invention discloses method for fabricating a MOSFET on a substrate to improve device ruggedness.

Abstract: This invention discloses a MOSFET device in a semiconductor chip with a top surface and a bottom surface. The MOSFET device includes a drain region, doped with impurities of a first conductivity type, formed in the semiconductor chip near the bottom surface. The MOSFET device further includes a vertical pn-junction region, which includes a lower-outer body region, doped with impurities of a second conductivity type, formed on top of the drain region. The pn-junction region further includes a source region, doped with impurities of the first conductivity type, formed on top of the lower-outer body region wherein the lower-outer body region defining a channel region extending from the source region to the drain region near the top surface. The MOSFET device further includes a gate formed on top of the channel region on the top surface. The gate includes a thin insulative bottom layer for insulating from the channel region.

Abstract: The present invention discloses a MOSFET transistor supported on a substrate. The MOSFET transistor includes an epitaxial-layer of a first conductivity type near a top surface of the substrate defining a drain region therein. The MOSFET transistor further includes an oxide block supported on a raised silicon terrace of the epitaxial layer disposed in a central portion of the transistor above a JFET reduction region of a first conductivity type of higher dopant concentration than the epitaxial layer. The MOSFET transistor further includes a lower-outer body region of a second conductivity type surrounding the JFET reduction region disposed near the top surface and defining a boundary of the MOSFET transistor. The MOSFET transistor further includes a source region of the first conductivity type enclosed in the lower-outer body region disposed near the top surface and extended to the transistor boundary.

Abstract: This invention discloses a MOSFET device which includes a plurality of vertical cells each includes a source, a drain, and a channel for conducting source-to-drain current therethrough. Each of the vertical cells is surrounded by a polysilicon layer acting as a gate for controlling the source-to-drain current through the channel. The MOSFET device further include a plurality of doping trenches filled with trench-filling materials, The MOSFET device further includes a plurality of deep-doped regions disposed underneath the doping trenches wherein the deep-doped region extends downwardly to a depth which is substantially a sum of an implant depth of the deep-doped region and a vertical diffusion depth below a bottom of the doping trenches.

Abstract: The present invention discloses a power transistor disposed on a substrate. The power device includes a core cell area comprising a plurality of power transistor cells each having drain and a source. Each of the power transistor cells further having a polycrystalline silicon gate formed on the substrate as part of a polycrystalline silicon gate layer overlaying the substrate. The polycrystalline silicon gate layer includes a plurality of polycrystalline gate-layer-extension extending to gate contact areas for forming gate contacts with a contact metal disposed thereon. The power transistor further includes a plurality of contact-metal-resistant pad each includes a thick oxide pad disposed below the gate contact areas underneath the polycrystalline gate layer extension whereby the contact-metal resistant pads resists the contact metal from penetrating therethrough and short to the substrate disposed thereunder.

Abstract: The present invention discloses a power transistor disposed on a substrate. The power device includes a core cell area comprising a plurality of power transistor cells each having drain and a source. Each of the power transistor cells further having a polycrystalline silicon gate formed on the substrate as part of a polycrystalline silicon gate layer overlaying the substrate. The polycrystalline silicon gate layer includes a plurality of polycrystalline gate-layer-extension extending to gate contact areas for forming gate contacts with a contact metal disposed thereon. The power transistor further includes a plurality of contact-metal-resistant pad each includes a thick oxide pad disposed below the gate contact areas underneath the polycrystalline gate layer extension whereby the contact-metal resistant pads resists the contact metal from penetrating therethrough and short to the substrate disposed thereunder.

Abstract: Improved power MOSFET structure, and fabrication process are disclosed in this invention to achieve higher breakdown voltage and improved device ruggedness. The power transistor includes a core cell area which includes a plurality of power transistor cells and a termination area. The power transistor further includes an outer pickup guarding ring, disposed in the termination area guarding the core cell area, for picking up free charged-particles generated in the termination area for preventing the free charged particles from entering the core cell area. In another preferred embodiment, the power transistor further includes an inner pickup guarding fence and blocks, disposed between the termination area and the core cell area for picking up free charged-particles not yet picked up by the outer pickup guarding ring for preventing the free charged particles from entering the core cell area.

Abstract: The present invention discloses a trenched DMOS device supported on a substrate of a first conductivity type including a core cell area which includes at least a trenched DMOS cell having a gate disposed in a trench and a drain region disposed in the substrate, the substrate further includes a termination area which includes at least a channel-stop trench. The trenched DMOS cell includes a source region of the first conductivity type extending from the top surface of the substrate adjacent to the trenches in the substrate. The trenched DMOS cell further includes a body region of a second conductivity type of opposite polarity from the first conductivity type, the body region extends from the top surface surrounding the source region adjacent the trenches in the substrate. The trenched DMOS device further includes an insulating layer lining the trenches and a conductive material filling the trenches.

Abstract: The present invention discloses a power transistor cell supported on a semiconductor substrate with a top surface and a bottom surface. The power transistor cell includes a drain region, doped with impurities of a first conductivity type, formed at the bottom surface. The power transistor cell further includes a polysilicon gate layer overlaying the top surface includes a polysilicon opening disposed substantially in a central portion of the transistor cell with a remaining portion of the polysilicon layer constituting a gate and defining an outer boundary for the transistor cell wherein the polysilicon opening and the outer boundary defined by the gate for the transistor cell constituting substantially non-orthogonal parallelograms. The power transistor further includes a source region, doped with the first conductivity type, disposed in the substrate underneath and around an outer edge of the source opening with a small portion extends underneath the gate.

Abstract: A power semiconductor device having internal circuits characterized by an electrical breakdown during one mode of operation is implemented with a protective circuit. The electrical breakdown is controllably induced to occur at the protective circuit thereby diverting any breakdown in the active circuits. In the preferred embodiment, the power device is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in which the protective circuit is deposited as an annular diffusion ring having a shallow portion and a deep portion. The deep portion is higher in doping concentration than the shallow portion and includes a radius of curvature larger than the shallow portion. The radius of curvature of the deep portion can be adjusted to induce breakdown at or above the rated value of the MOSFET. The predetermined doping concentration of the deep portion can abort the breakdown prematurely to occur at the deep region instead of at the active circuits.

Abstract: A n-channel MOSFET device is formed with a selective high energy boron implantation into the N region of the n- channel where a photoresist is employed to cover the central portion over the channel. Small n- regions are formed near the channel source interface. These small n- regions have the advantages of preventing punch through. The selective implant regions have the additional advantages that the JFET resistance is not increased as a result of forming a punch through prevention region near the source channel boundary. Also disclosed in this invention is a p-type DMOS where a novel boron implantation is applied to reduce the threshold voltage. The boron is selectively implanted into the n-type channel near the source, i.e., a threshold sensitive region. The threshold voltage is reduced without unduly lowering the drain to source breakdown voltage.

Abstract: Improved power MOSFET structure, and fabrication process are disclosed in this invention to achieve a low threshold voltage. The improved MOSFET device is formed in a semiconductor substrate with a drain region formed near a bottom surface of the substrate supporting a plurality of double-diffused vertical cells thereon wherein each of the vertical cells including a pn-junction having a body region surrounding a source region and each of the vertical cell further including a gate above the pn-junction. Each of the vertical cells further includes a source-dopant segregation reduction layer for reducing a surface segregation between the source region and an oxide layer underneath the gate whereby the body surface peak dopant concentration near an interface between the source region and the body region is reduced for reducing a threshold voltage of the MOSFET device.

Abstract: A new DMOS fabrication process is disclosed.