Abstract: A data-processing system with an enhanced system controller supporting memory-remapping function. The system controller has an access control circuit, a page/remapping management circuit and an open/remapped address table. The open/remapped address table is used to store mapping tables for indicating the mapping relation of memory segments and addresses dedicated to peripheral devices. The page/remapping management circuit should maintain and use the mapping tables in various operating mode. In addition, the page/remapping management circuit can redirect access requests to proper memory segments according to the mapping table corresponding to the current operating mode. Therefore, peripheral devices can effectively access and process the data stored in various memory segments by the change of the operating modes, not by physical data transfer.

Abstract: A system and method for reducing data traffic between the processor and the system controller in a data processing system during the execution of a vector or matrix instruction. When the processor receives an operation command requiring that a large quantity of data be processed, the processor issues a local operation request containing the desired operation, addressing information of the operands and a destination location for the result to the system. The system controller includes a local operation unit for locally executing the local operation request issued from the processor. Because the operand data associated with the operation need not be transferred over the system bus connected between the processor and the system controller, the data traffic between the processor and the system controller is reduced.

Abstract: A buffer management device and method for improving buffer usage and access performance in a data processing system. A buffer device is located between two components in the data processing system and can be operated in the line mode and page mode. The buffer device typically comprises a number of memory blocks for temporarily storing the transmitted data, first tag memories, second tag memories and a mode-switching circuit. Each of the memory blocks includes a plurality of memory segments. In the line mode, the first tag memories store the addressing information and the memory blocks serve as the data storage unit. In the page mode, the second tag memories store the addressing information and the memory segments serve as the data storage unit. Therefore, data carried by different requests can be merged into the same memory block.