Abstract: An editing tool that provides a user interface for displaying and editing a representation of a microcircuit design. More particularly, the user interface displays a three dimensional representation of a second portion of the circuit design. A user can then select and edit a structure employing the three-dimensional representation of the structure in the user interface.

Abstract: A PG wire routing optimization tool for more efficiently routing PG wires in a layout design of an integrated circuit. The PG wire routing optimization tool analyzes a routing of the wires of a power and ground network for unacceptable IR-drops or electromigration problems. If one or more problems are discovered, the PG wire routing optimization tool determines design constraints for the wires that will correct the identified problems. It then initiates a floor planning tool to implement these corrective design constraints in the floor plan design. The PG wire routing optimization tool may alternately or additionally determine design constraints that will minimize the area of the wiring but will avoid creating new IR-drop or electromigration problems. It will then initiate a floor planning tool to implement these optimizing design constraints in the floor plan design.

Abstract: A tool for emulation systems that obtains the state values for only discrete partitions of a circuit design. When a partition is being emulated, the emulation system obtains the input values for the specified partition at each clock cycle and the state values for the specified partition at intervals. Using the state and input values with a software model of the specified circuit design partition, the tool calculates the state values for the partition at every clock cycle. The software model may correspond to the partitioning information used to implement the circuit design across multiple configurable logic element devices, such as FPGAs. Thus, each software model may correspond to the portion of a circuit design emulated on a discrete FPGA integrated circuit.

Abstract: Related communication signals between a simulator and an emulator are organized into logical channels. The signals in each channel are then be transmitted only as needed, reducing the use of the communication pathways between the simulator and the emulator. Further, the circuit components that will receive the communication signals to be shared on a channel are be physically located close together within the emulator, thereby reducing the time required to select and enable components of the emulator to receive the signals sent by the simulator. Similarly, emulator components that send communication signals to be shared on a channel are physically located close together within the emulator, thereby reducing the time required to select and enable components of the emulator to send these signals to the simulator.

Abstract: Techniques are disclosed for modifying an existing microdevice design to improve its manufacturability. With these techniques, a designer receives manufacturing criteria associated with data in a design. The associated design data then is identified and provided to the microdevice designer, who may choose to modify the design based upon the manufacturing criteria. In this manner, the designer can directly incorporate manufacturing criteria from the foundry in the original design of the microdevice.

Abstract: A tool that a user may employ to assemble the components of a circuit in a floor plan design. The tool provides a user interface that displays the placement of blocks in a floor plan design, and the routing of wires among the blocks. When the designer moves the placement of a target block, the user interface automatically moves any adjacent blocks that would impede the movement of the target block and any block that would impede a block moved in response to the movement of the target block. The user interface may also respond to movement of a target block by showing how various features of the circuit will change as a result of the move. Thus, the user interface may show that moving one block closer to another block will create undesired wiring congestion in the circuit. The user interface also may show when moving a block will result in wiring connections that are too long to maintain a desired voltage level.

Abstract: A technique is provided for determining a hierarchical effectiveness for a cell in a data structure. The hierarchical effectiveness indicates how effective the use of the cell will be in executing a task with the data structure. A technique is also provided for determining the hierarchical effectiveness of all of the cells in a data structure, to determine which cells should be employed to execute a task with the data structure.

Abstract: Techniques are disclosed for modifying an existing microdevice design to improve its manufacturability. With these techniques, a designer receives manufacturing criteria associated with data in a design. The associated design data then is identified and provided to the microdevice designer, who may choose to modify the design based upon the manufacturing criteria. In this manner, the designer can directly incorporate manufacturing criteria from the foundry in the original design of the microdevice.

Abstract: A behavioral synthesis tool that allows a designer to design an integrated circuit using a generic programming language, such as ANSI C or C++, without the need to include timing information into the source code. In one aspect, the source code is read into the behavioral synthesis tool and the user may dynamically allocate interface resources to the design. In another aspect, the dynamic allocation is accomplished through user input, such as a GUI, a command line, or a file. In another aspect, the behavioral synthesis tool automatically analyzes variables in the source code description and assigns the variables to interface resources. In yet another aspect, the variables and interface resources associated with the variables may be displayed in a hierarchical format in a GUI. In still another aspect, the GUI may allow for expanding and collapsing of different layers in the hierarchy. The GUI may also allow for drag-and-drop operations for modifying the allocation of variables to interface resources.

Abstract: A tool is described herein for optimizing the design of a hardware-software system. The tool allows a designer to evaluate the potential improvement in system performance that may be realized by moving selected software components of the system to a hardware implementation. In one aspect, the tool automatically generates a performance profile of an original form of the system. The performance profile of the original form of the system may be used to select software components of the system to be moved to hardware. In another aspect, the tool generates an estimated performance profile of a repartitioned form of the system by modifying the performance profile of the system. The estimated performance profile of the repartitioned system is compared to the performance profile of the original form of the system to verify benefits, if any, of repartitioning. Such verification is accomplished without the need to actually repartitioning the system or measuring the performance of the entire repartitioned system.

Abstract: A hardware-software system design optimization tool is described. The tool allows a designer to optimize the system performance by allowing him to select software components of the system and move them to a hardware representation. The software components are selected by using a performance profile of the system, which comprises time data related to execution of the software components, memory and bus transactions. In another aspect, the tool automatically collects the performance data and generates the performance profile. In another aspect, performance data is collected by modeling the execution of the hardware-software system. In another aspect, hardware-software system is modeled again after selected software components are moved to a hardware representation to inquire whether the move improved overall system performance.

Abstract: A method and tool are disclosed for distributing operations in a software application from a master computer to one or more slave computers for execution. Operations within the software application are identified that employ input data independent of other input data. The identified operations, which can be organized into groups of one or more operations, may then be distributed to a slave computer for execution. A group of operations may also include one or more heuristics, for determining when the group of operations should be executed on a slave computer. If a group of operations is distributed to a slave computer for execution, the master computer subsequently determines if the slave computer successfully executed those operations. If the slave computer successfully executed the group of operations, it returns the results to the master computer, which then employs the returned results to continue running the software application.

Abstract: A regionally time multiplexed emulation system includes an emulator for emulating a circuit design. The emulator includes a plurality of reconfigurable logic devices with buffered I/O pins and reconfigurable logic elements. The reconfigurable logic devices are reconfigurable to emulate a circuit design using at least one user clock to clock the logic elements and at least one signal routing clock to time multiplex the routing of emulation signals between the reconfigurable logic devices, with the at least one signal routing clock being independent of the at least one user clock.

Abstract: Layout correction is accomplished using a forward mapping technique. Forward mapping refers to mapping of fragments from a reticle layout to a target layout, while backward mapping refers to mapping of fragments from the target layout to the reticle layout. Forward mapping provides a technique for making an unambiguous mapping for each reticle fragment to a corresponding target layout fragment. The mapping does not necessarily provide a one-to-one correspondence between reticle fragments and target layout fragments. That is, multiple reticle layout fragments can map to a single target layout fragment. An edge placement error for the target layout fragments is used to make positioning corrections for the corresponding reticle fragment(s). Edge placement error can be determined, for example, with a simulation process that simulates a manufacturing process using the reticles.