Abstract: Disclosed are techniques for correcting the EUV crosstalk effects. Isolated mask feature component diffraction signals associated with individual layout feature components are determined based on a component-based mask diffraction modeling method such as a domain decomposition method. Mask feature component diffraction signals are then determined based on the isolated mask feature component diffraction signals, layout data and predetermined crosstalk signals. Here, the predetermined crosstalk signals are derived based on mask feature component diffraction signals computed using an electromagnetic field solver and the component-based mask diffraction modeling method, respectively. The mask feature component diffraction signals are then used to process layout designs.

Abstract: Techniques and mechanisms for marking the parameters of a circuit analysis process for visual identification are disclosed. The visually-identified parameters can then be employed with the results of the circuit analysis to debug the layout design.

Abstract: This application discloses a video inspection system for a rework station, which includes multiple image capture devices to capture multiple images or videos of a printed circuit board assembly, a presentation tool to merge the captured images or video into a image or video, and a display device to present the image video. The presentation tool also can augment the captured video of the printed circuit board assembly with information from a layout design of the printed circuit board assembly. The presentation tool can receive a selection of a portion of the layout design or a selection of at least one component in the printed circuit board assembly, and annotate the captured video of the printed circuit board assembly with design data from the layout design that corresponds to the selected portion of the layout design or the selected component in the printed circuit board assembly.

Abstract: This application discloses a computing system configured to perform a pre-linked embedding process during build-time of a root-kernel application. The computing system can pre-link one or more dynamically-linkable executable modules against exported symbols of a root-kernel image, and embed the pre-linked executable modules into the root-kernel image. The computing system can load the root-kernel image having the embedded pre-linked executable modules into a memory of an embedded system, wherein at least one processing device in the embedded system is configured to execute the embedded pre-linked executable modules directly from the memory.

Abstract: This application discloses a computing system to identify portions of source code in a test bench that correspond to class objects, and insert handle tracking code at locations in the test bench associated with the identified portions of source code. During simulation of the test bench, the computing system can execute the handle tracking code, which generates handle occupancies corresponding to memory pointers associated with the class objects. Each of the handle occupancies can include a handle reference or memory pointer for a class object, a location in the test bench corresponding to usage of the memory pointer, and a simulation time associated with the generation of the handle occupancy. The computing system can arrange the handle occupancies, synchronize the handle occupancies to portions of source code in the test bench, and display the handle occupancies and the test bench source code in a debug window.

Abstract: Aspects of the disclosed technology relate to techniques of full-chip assessment of time-dependent dielectric breakdown. A layout design is analyzed to identify matching patterns that match a pre-calculated pattern in a pattern database. Each of pre-calculated patterns in the pattern database has a time-to-failure characteristic value pre-computed based on a model of electric current path generation and evolution. Time-to-failure characteristic values are then determined for the matching patterns based on the pre-computed time-to-failure characteristic values and electric attributes of geometric elements in each of the matching patterns. Based on the time-to-failure characteristic values, matching patterns most susceptible to time-dependent dielectric breakdown are identified and fixed.

Abstract: A method and apparatus for translating a hierarchical IC layout file into a format that can be used by a mask writer that accepts files having a limited hierarchy. Cover cells of the original IC layout file or a modified file are designated, and the hierarchical file is redefined to include only those designated cover cells. Non-designated cover cells and other geometric data are flattened into the designated cover cells. The hierarchy of the modified file is then redefined to be less than or equal to the hierarchy limit of the mask writing tool.

Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

Abstract: Aspects of the disclosed technology relate to techniques for corrupting memories in emulation. After a power domain in a circuit design being emulated in an emulator is powered down, a main memory model for a memory in the power domain is corrupted and a cache memory model for the memory is invalidated. The cache memory model is a hardware model in the emulator and the main memory model is a software model in a workstation coupled to the emulator. The cache memory model stores a subset of data that are stored in the main memory model. The combination of the main memory model and the cache memory model is used to model the memory.

Abstract: This application discloses a computing system implementing tools and mechanisms that can incorporate a security co-processor into a circuit design modeling an electronic device. The tools and mechanisms can configure the security co-processor to monitor at least a portion of the electronic device. The tools and mechanisms can generate at least one security action for the security co-processor to initiate when the security co-processor monitors the electronic device failing to conform to rules in a rules database.

Abstract: This application discloses a computing system configured to request that an operating system implemented by the computing system allocate a virtual address space, which is designated for use by an application implemented by the computing system, to a memory verification tool implemented by the computing system. The computing system is configured to utilize the virtual address space to form a memory pool having multiple protectable slots available for allocation to the application. The computing system is further configured to intercept a memory allocation request issued by the application to the operating system of the computing system, and allocate at least one of the protectable slots in the memory pool to the application in response to the intercepted memory allocation request.

Abstract: Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.

Abstract: Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. Such embodiments can be used to generate a “complete” test set—that is, a set of chain diagnosis test patterns that is able to isolate any scan chain defect in a faulty scan chain to a single scan cell.

Abstract: A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.

Abstract: Embodiments of the disclosed technology comprise a cloud-hosted central service platform that interfaces and enables access to both central and distributed resources and peripherals for connected mobile applications. For example, this platform allows service providers and application developers to create a large number of new classes of applications, leveraging web access to devices, sensors, and/or actuators of any kind. This platform can be applied to virtually any vertical segment. Any of the disclosed features or aspects of the disclosed embodiments can be used in various combinations and subcombinations with one another or with other methods, apparatus, and systems.

Abstract: Aspects of the disclosed technology relate to techniques of design implementation for FPGA prototyping. An initial FPGA-mapped netlist and a generic RTL design associated with the initial FPGA-mapped netlist are generated based on an original RTL (register-transfer level) design for a circuit design and optionally on verification-related features. Based on the initial FPGA-mapped netlist, the circuit design is partitioned into design partitions for implementing the circuit design across a plurality of FPGA chips. Final FPGA-mapped netlists are then generated based on the design partitions represented by the generic RTL design or by a combination of the generic RTL design and the initial FPGA-mapped netlist.

Abstract: Aspects of the invention relate to techniques for dynamic control of design clock generation in emulation. A circuit design for verification is analyzed to determine one or more clock-enabling functions for a specific clock signal. Logic for generating a clock status signal based on the one or more clock-enabling signals is then determined. The clock status signal is employed to control clock generation in an emulation system for emulating the circuit design.

Abstract: This application discloses a computing system implementing one or more tools or mechanism configured to capture a hierarchy of a circuit design layout generated by a downstream tool. The hierarchy can include multiple cells that identify corresponding portions of the circuit design layout. The tools or mechanism can be further configured to modify the circuit design layout based, at least in part, on the captured hierarchy, which alters the portions of the circuit design layout identified by the cells separately from other portions of the circuit design layout.

Abstract: Various aspects of the disclosed technology relate to deterministic built-in self-test. A deterministic built-in self-test system comprises: a decompressor configured at least to decompress one of compressed test patterns stored on chip for a predetermined number of times; and a controller configured at least to output a control signal that inverts outputs of the decompressor at one or more scan shift clock cycles based on control data stored on chip, enabling the system to output the predetermined number of test patterns based on the one of compressed test patterns, wherein the one or more scan shift clock cycles are different for each of the predetermined number of test patterns.

Abstract: Techniques for employing an additive design process to design heat sinks are disclosed. A heat sink “grows” through an iteration process. During each iteration step, an object is added to a location determined based on simulation. The criterion for the determination may be being a location having a highest fluid apparent surface temperature value or being a location having a highest bottleneck heat transfer characteristic value. The thermal performance of the newly derived structure is simulated. If a predetermined condition is met, the object is kept. Otherwise, the object is removed and the location is marked so that the same addition may not occur subsequently. The iteration process may be repeated.