Abstract: The invention is a method of forming a solder bump on an under bump metallurgy in which a contact pad on a substrate material is partially covered by a passivation layer upon the substrate material which is non-wettable by solder and in which the under bump metallurgy covers the portions of the contact pad which are not covered by the passivation layer and in which the under bump metallurgy overlaps from the contact pad to cover portions of the passivation layer.

Abstract: A method of soldering without the need for fluxing agents, high temperature, hydrogen, laser excitation or sputtering techniques. The method uses plasma excitation to remove surface oxides from solder surfaces, thereby eliminating the need for post-soldering cleaning in an accurate and efficient manner, resulting in a higher quality and long term reliability solder joint. In addition, serious environmental problems caused by cleaning solvents are avoided.

Abstract: An array wand for charged particle beam shaping and control applications can selectively and accurately shape or deflect single or multiple beams of charged particles so as to delineate a desired pattern in a substrate. The wand preferably takes the form of a monolithic block of material, for example semiconductor material, having one or more cavities etched through it which serve to form a collimated beam of particles. The array wand employs an Einsel lens structure which contains electrostatic electrodes for precise focusing of the beams of charged particles. The Einsel lens includes successive layers on the monolithic substrate which simultaneously act as a lens, an aperture, and a beam line for beams of charged particles.The array wand may be manufactured, in large quantity with precision, and may be employed to form small focused beams.

Abstract: A variable threshold logic detector with high switching speeds and small circuit size is disclosed. The device utilizes transistors of opposite semiconductor materials to provide a large change in voltage when a certain current threshold or number of inputs has been crossed. The number of inputs that may be accommodated and the current threshold are variable and each input may be individually weighted.

Abstract: A method of forming a nonsilicon semiconductor layer on an insulating layer by forming a thin heteroepitaxial layer of nonsilicon semiconductor on a first substrate having a lattice structure which matches that of the heteroepitaxial layer. A first insulating layer is formed on the heteroepitaxial layer. A second insulating layer is formed on the surface of a second substrate. The first and second insulating layers are bonded together to form a unified structure, and the first substate is etched away. In a preferred embodiment the heteroepitaxial layer is germanium, gallium arsenide or silicon-germanium alloy while the first substrate is silicon, germanium, gallium arsenide or silicon-germanium alloy.

Abstract: A method for anisotropically hardening a protective coating to provide a well defined edge thereon for forming features which may be smaller than the resolution limit of the exposure equipment for the purpose of integrated circuit manufacture is disclosed. The method includes the steps of forming a non-planar coating on a substrate with a photoresist material having a sensitivity to incident flux that varies as a function of the angle of the incidence of the flux upon the coating. The coating is anisotropically hardened by exposing it to flux to which it has a relatively high sensitivity so that portions for which the flux is incident at one angle are more hardened than those portions where the flux is incident at a different angle.

Abstract: Miniature electric assembly for isolating voltage referenced transmission lines and method for producing it, the assembly comprising a lower conductive reference layer conforming to the upper surface of the planar substrate a conductor, a first or lower dielectric layer encasing and supporting the conductor along its length above the surface of the lower conductive reference layer, a second or middle dielectric layer, an upper conductive reference layer covering the first dielectric layer and encasing the conductor and the first and second dielectric layer along their lengths; and a third or upper dielectric layer covering the upper conductive reference layer.

Abstract: Apparatus for mounting a semiconductor device chip and making electrical connections thereto is disclosed. A semiconductor device chip has its backside connected to the surface of a substrate, and its upper surface includes a plurality of electrical pads across the entire surface thereof. A translator chip having a plurality of first electrical contacts disposed generally across the interior portion thereof are in electrical contact with the semiconductor device chip electrical pads, and a plurality of second electrical contacts disposed generally around the perimeter of the translator chip are electrically connected with the electrical terminals in the substrate to which the chip is attached. Heat may be removed from the semiconductor device chip through its backside via cooling channels in the substrate.

Abstract: A microelectronics apparatus and a method of fabricating customized connections between wiring planes superposed on a substrate is disclosed. A first wiring plane having multiple conductors is formed upon the substrate. An insulating layer is formed that overlies and electrically insulates the first wiring plane. A second wiring plane having multiple conductors is formed above the insulating layer by forming multiple conductors that are electrically connected to the first wiring plane with selected conductors of the first wiring plane being electrically connected to selected conductors of the second wiring plane. The connections may be modified by breaking selected ones of the electrical connections between the first and second wiring planes to customize the electrical interconnections.

Abstract: A shared current loop, multiple field apparatus and process for magnetron gas discharge processing is disclosed. The apparatus includes an evacuable chamber for containing a reactant gas. A multi-part cathode associated with a current loop generates multiple, independent electrical fields. The cathode comprises a first cathode portion for generating a first electric field that forms a gas discharge including ions. The second cathode portion generates a second, independent electric field. The second electric field extracts ions from the gas discharge, and may also control the energy with which the extracted ions strike an item to be processed. Each cathode portion is electrically insulated from the other and may be connected to a separate power source.

Abstract: A staining technique for specimens which involves the sequential treatment of specimens with periodic or hydrochloric acid, thiocarbohydrazide or thiosemicarbazide, and silver methenamine. The technique, when using periodic acid, provides an excellent stain to evaluate glycomacromolecules and fibrovascular tissue and to conduct a broad spectrum of staining procedures for all modes of microscopy. Use of hydrochloric acid facilitates evaluation of cell nuclear DNA and chromatin.

Abstract: A microelectronics apparatus and a method of fabricating customized connections between wiring planes superposed on a substrate is disclosed. A first wiring plane having multiple conductors is formed upon the substrate. An insulating layer is formed that overlies and electrically insulates the first wiring plane. A second wiring plane having multiple conductors is formed above the insulating layer by forming multiple conductors that are electrically connected to the first wiring plane with selected conductors of the first wiring plane being electrically connected to selected conductors of the second wiring plane. The connections may be modified by breaking selected ones of the electrical connections between the first and second wiring planes to customize the electrical interconnections.

Abstract: A method and apparatus are disclosed for exposing photoresist using an incident electron beam during the fabrication of a semiconductor device. The method includes the steps of coating the substrate with a photoresist that is exposed in response to an electron beam. An electron beam is projected onto the photoresist and deflected to trace a pattern. The voltage and the amount of charge of the electron beam are controlled as it is deflected so that the energy incident upon the coated photoresist is correlated to variations in the photoresist thickness to expose the photoresist with minimal penetration therethrough to underlying structures.