Patents Assigned to Micron Techology, Inc.
  • Patent number: 11557326
    Abstract: The present disclosure includes apparatuses and methods related to bank coordination in a memory device. A number of embodiments include a method comprising concurrently performing a memory operation by a threshold number of memory regions, and executing a command to cause a budget area to perform a power budget operation associated with the memory operation.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: January 17, 2023
    Assignee: Micron Techology, Inc.
    Inventors: Kelley D. Dobelstein, Jason T. Zawodny, Kyle B. Wheeler
  • Patent number: 11074955
    Abstract: Methods, systems, and devices for cell voltage accumulation discharge are described. One or more sections of a bank of ferroelectric memory cells may be coupled with one or more access lines. By activating one or more switching components, one or more sections (that may include a memory array and/or a driver) of memory cells may be isolated. When isolated, a voltage may be applied across an access line associated with the section to activate an access device of each memory cell. By activating a switching component of a respective memory cell, a capacitor of the memory cell may be discharged and then the isolated section may be coupled with the plurality of access lines.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: July 27, 2021
    Assignee: Micron Techology, Inc.
    Inventors: Adam S. El-Mansouri, David L. Pinney
  • Patent number: 9705318
    Abstract: Protection circuits and methods for protecting an integrated circuit against an over-limit electrical condition are provided. One example includes a snapback circuit having at least a portion formed in an isolated doped well region and configured to switch to a low impedance state in response to an input exceeding a trigger condition and further having a control circuit coupled to a reference voltage and further coupled to the isolated doped well region and the portion of the snapback circuit formed in the doped well region. The control circuit includes an impedance adjustable in response to a control signal and configured to adjust an isolated doped well impedance in which at least a portion of the snapback circuit is formed relative to the reference voltage. A modulated trigger and hold condition tot the snapback circuit can be set according to a control signal adjusting an electrical impedance of the control circuit.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: July 11, 2017
    Assignee: Micron Techology, Inc.
    Inventors: Michael Chaine, Xiaofeng Fan
  • Patent number: 6850244
    Abstract: A method and system for providing surface texture in a graphics image rendered by a graphics processing system. Color values of a pixel having a normal vector normal to a surface in which the pixel is located are calculated based on a perturbed normal vector. The perturbed normal vector is displaced from the normal vector by a displacement equal to the sum of a first vector tangent to the surface at the location of the pixel scaled by a first scale factor and a first displacement value, and a second vector tangent to the surface at the location of the pixel and scaled by a second scale factor and a second displacement value, the second vector perpendicular to the first vector. The displacement values are representative of partial derivatives of a function defining a texture applied to the surface and the scale factors are used to scale the magnitude of the resulting perturbed normal. The color value for the pixel being rendered will be based on the perturbed normal vector instead of the normal vector.
    Type: Grant
    Filed: January 11, 2001
    Date of Patent: February 1, 2005
    Assignee: Micron Techology, Inc.
    Inventors: Aaftab Munshi, Colin Sharp
  • Patent number: 6784046
    Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.
    Type: Grant
    Filed: March 22, 2002
    Date of Patent: August 31, 2004
    Assignee: Micron Techology, Inc.
    Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme
  • Publication number: 20030003697
    Abstract: Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient.
    Type: Application
    Filed: August 21, 2002
    Publication date: January 2, 2003
    Applicant: Micron Techology, Inc.
    Inventors: Vishnu K. Agarwal, Garo Derderian, Gurtej S. Sandhu, Weimin M. Li, Mark Visokay, Cem Basceri, Sam Yang
  • Patent number: 5217369
    Abstract: An improved apparatus is described for the closure of the open end of a conventional tube furnace used in the treatment of semiconductor devices manufactured in the integrated circuit industry. The apparatus consists primarily of an adjustable fixed weight on one end of a lever arm and a roller bearing means on the other end, said lever arm being supported by a fulcrum structure which is adjustably attached to the movable track which transports the semiconductor devices into and out of the furnace. The roller bearing end of the lever arm rests with constant pressure against the rear face of the furnace door when the door is closed and held against the opening in the tube furnace. The design eliminates the need for springs and is insensitive to the environment.
    Type: Grant
    Filed: May 28, 1992
    Date of Patent: June 8, 1993
    Assignee: Micron Techology, Inc.
    Inventors: Dix Brown, Nathan P. Lee, Willard L. Hofer
  • Patent number: 5095736
    Abstract: The present invention relates to a portable gas cylinder safety containment system removably and operably incorporated with a portable, self powered, toxic gas monitoring system, and both removably attached to a delivery cart system, to provide real time monitoring of the delivery cart contents while in transit. This system is designed particularly for the safe transport between storage and work areas of toxic and hazardous gases used in various research, laboratory and production process, such as those in the semiconductor and microcircuit industries.
    Type: Grant
    Filed: May 10, 1990
    Date of Patent: March 17, 1992
    Assignee: Micron Techology, Inc.
    Inventors: Richard Fesler, Jim Nielsen