Abstract: The method for programming non-volatile memory cells erases the memory cells to be programmed. The memory cells are then programmed to a reduced floating gate voltage that takes into account capacitive coupling between the floating gates of adjacent memory cells. In one embodiment, the programming method programs and verifies a first memory cell to the reduced floating gate voltage, programs and verifies an adjacent memory cell to the reduced floating gate voltage, and verifies the first memory cell to an increased floating gate voltage that is greater than the reduced floating gate voltage.

Abstract: A method of forming an SRAM cell includes, a) providing a pair of pull-down gates having associated transistor diffusiion regions operatively adjacent thereto, one of the diffusion regions of each pull-down gate being electrically connected to the other pull-down gate; b) providing a pair of pull-up resistor nodes for electrical connection with a pair of respective pull-up resistors, the pull-up nodes being in respective electrical connection with one of the pull-down diffusion regions and the other pull-down gate; c) providing a first electrical insulating layer outwardly of the reistor nodes; d) providing a pair of contact openings, with respective width, through the first insulating layer to the pair of resistor nodes; e) providing a second electrical insulating layer over the first layer and to within the pair of contact openings to a thickness which is less than one-half the open widths; f) anisotropically etching the second electrical insulating layer to define respective electrical insulating annulus s

Abstract: There is an IC (integrated circuit) testing device 11 that receives singulated ICs from a singulation station's bottom table 44, where an IC 15 has slid down onto loading ramp or track 16. The IC will slide into test station 18, where stop pin 22 has been inserted to stop the IC in DUT (device under test) station 20. In the DUT station, the IC is securely held in position by an extractor bar 26, insertion bar 28, and a part guide 24. Thereby, test cite station 18 will move downward and insert IC 15 into testing socket 30. After testing the IC, testing station 18 returns upward with IC in the same secured position. Pin 22 will be removed to allow the IC to slide into part holding station 31. If the IC was not defective, pin 32 will be removed to allow the IC to slide onto track 36 of the IC separator station 34. While the test cite station 18 is in the up position a second IC is slid along track 16 and loaded into DUT cite 20 being readied for the next test cycle.